Is there a better description of the steps of the flow somewhere? I'm getting some signals disconnected between the output of user_project_wrapper.synthesized.v and user_project_wrapper.synthesized_optimized.v, but I'm not sure what step that actually corresponds to (4-Yosys?)
Actually, flow_summary.log might be this...
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Matt Venn
06/18/2021, 8:16 AM
you think maybe yosys is optimising out part of your design?
sometimes I've used (* keep *) to keep stuff in
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Matthew Guthaus
06/18/2021, 12:55 PM
I literally have two SRAMs, both connected directly to the LA in a test case, and the single port gets disconnected din/dout