Is there a better description of the steps of the flow somew

Question

Is there a better description of the steps of the flow somewhere I m getting some signals disconnected between the output of user project wrapper synthesized v and user project wrapper synthesized optimized v but I m not sure what step that actually corresponds to 4 Yosys

Matthew Guthaus · Answer

Actually flow summary log might be this

Matt Venn · Answer

you think maybe yosys is optimising out part of your design

Matt Venn · Answer

sometimes I ve used keep to keep stuff in

Matthew Guthaus · Answer

I literally have two SRAMs both connected directly to the LA in a test case and the single port gets disconnected din dout

Matthew Guthaus · Answer

This is that test case <https github com VLSIDA openram test project git>

Matthew Guthaus · Answer

I figured it out The LEF file for the single port macro had an extra pin and something just silently disconnected the entire din dout because of this

Matt Venn · Answer

so you are getting a result now

Matthew Guthaus · Answer

Kind of I need to fix OpenRAM and regenerate all the single port macros

Matthew Guthaus · Answer

May just hack it for now

Matt Venn · Answer

haaaaaaaakkk