open-source-silicon.dev

Is there a better description of the steps of the flow somewhere? I'm getting some signals disconnected between the output of user_project_wrapper.synthesized.v and user_project_wrapper.synthesized_optimized.v, but I'm not sure what step that actually corresponds to (4-Yosys?)

Actually, flow_summary.log might be this...

you think maybe yosys is optimising out part of your design?

sometimes I've used (* keep *) to keep stuff in

I literally have two SRAMs, both connected directly to the LA in a test case, and the single port gets disconnected din/dout

This is that test case:
<https://github.com/VLSIDA/openram_test_project.git>

I figured it out. The LEF file for the single port macro had an extra pin and something just silently disconnected the entire din/dout because of this

Kind of. I need to fix OpenRAM and regenerate all the single port macros