Hey folks. I have a design where I can scale the size of the circuit (add more units). At some point as I increase the amount of circuitry the design becomes unable to synthesize, with OpenLane reporting "too much congestion". Does anybody know any parameters I could tweak to possibly help with this? Would reducing the density by decreasing

PL_TARGET_DENSITY

and

FP_CORE_UTIL

help, or are those irrelevant to this "congestion"?

For the first, do you mean PL_TARGET_DENSITY? That causes placement to spread cells out to meet local density The FP_CORE_UTIL determines how much area a relative floorplan should be compared to the cell area. It doesn't matter if you have an absolute floorplan size. Last, your may want to restrict the GLB_ROUTE_ADJUSTMENT which will reserve some global route tracks to spread out wires. So, yes, all if the above.

Yes, sorry, I meant

PL_TARGET_DENSITY

. Cool, thanks, I'll try

GLB_ROUTE_ADJUSTMENT

.

Yes, that's what I meant. This reserves space in the global routing grid which will make the detailed routing easier. By default it doesn't reserve/reduce any so the global routing is at full capacity and can be hard to detailed route. You can also do this for specific layers

@Peter Schmidt-Nielsen If you have the time, you might also try increasing the iterations. I hear the default limit is 64.

Thanks folks for the suggestions. Setting

GLB_RT_ADJUSTMENT

to values like 0.2, 0.5, and 1 didn't have any discernible effect, but I increased

GLB_RT_OVERFLOW_ITERS

to 200 and

ROUTING_OPT_ITERS

to 256, and things got a tad better.