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Anmol

07/08/2021, 10:30 AM
Hello, I was trying to run OpenLane in interactive mode. I wanted to know the significance of the command "run_powered_verilog". What does it do?
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Mitch Bailey

07/08/2021, 12:04 PM
@Anmol I believe the run_powered_verilog step adds the power connections to the gate level verilog. This allows the verilog to be used for LVS. Before:
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sky130_fd_sc_hd__dfxtp_2 _880_ (
  .CLK(\counter.clk ),
  .D(_197_),
  .Q(io_out[31])
 );
After:
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sky130_fd_sc_hd__dfxtp_4 _880_ (
  .D(_197_),
  .Q(net430),
  .CLK(\clknet_1_1_0_counter.clk ),
  .VGND(vssd1),
  .VNB(vssd1),
  .VPB(vccd1),
  .VPWR(vccd1)
);
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Anmol

07/08/2021, 12:13 PM
Thanks