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Hello to all, I have one question about macro hard...
# openlane
k
Hello to all, I have one question about macro hardening. What I would to do is to harden a few macros on my top level module and then, generate a macro of the top module, which I would like to integrate with caravel harness (Chip Hardening). The question itself is, if the methodology based on hierarchical macro hardening is correct ? I suppose it is possible however I would like to be 100% sure.
m
that sounds right. You can't have any logic in your top level (user_project_wrapper), only wires. So pre-harden everything first, then instantiate and connect them in user_project_wrapper
k
Hi Matt, thank You for your suggestions. FInally I have had some errors due to the open road bug. With a help of @mehdi i I got it working using custom interactive script
Respect to the Wishbone communication (other thread) I have seen Your video. I use very similar solution that You show however the problem is in the hierarchies. In fact my slave has 2 levels (see figure) and there are multiple modules sub-slaves that read and write to the WB. The problem I have found is about contention where all subslaves write to the WB on the write cycle. I can see two solutions: (1) implementar address decoder and multiplex the wb_data_o and wb_ack_o between subslaves or (2) implement it (withiin the subslave) as high-Z.. Do You have any thoughts on this ? Appreciate Your help. Regards
hierearchy.drawio(1).png
upw
upw
this is the layout of the user_project_wrapper
m
I would go for address decoder and tristate outs
k
I thing I wil try out the tristates
m
But if you do this you have to turn off output buffering, otherwise your tristate will be followed by a clock buffer
Other disadvantage is can't run on fpga
k
in which step I can disable the buffereing?
m
Check the wrapper.v and config
k
ok, thank You!\
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set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
suppose is that one
one more question. Do You know how to het the value of the load and driving cell names for the ports specified in the user project wrapper I mean all the wb ports, LA ports and also external IO. I would like to perform STA and those values are needed
m
One for @Tim Edwards ?
t
Look at the gate-level netlists for the corresponding cells in the Caravel repository. The logic analyzer ports are in 
verilog/gl/mgmt_protect.v
and the I/O ports are in 
verilog/gl/gpio_control_block.v
. e.g., data input to the user project from the LA is 
la_data_in_mprj
(output from 
mgmt_protect.v
) and the driving cell is a 
sky130_fd_sc_hd__inv_8
. There are only three pins connected to the user area in 
gpio_control_block.v
, which are 
user_gpio_oeb
, 
user_gpio_out
, and 
user_gpio_in
, connected to 
sky130_fd_sc_hd__mux2_1
(load) for the first two, and 
sky130_fd_sc_hd__einvp_8
(driving) for the last one.
k
cool, very clear Thank You Tim
@Matt Venn Hi Matt, I am facing a strange behavior of Yosys when I am making logic synthesis of my design. In particular it get stucked here
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15.1. Executing Verilog-2005 frontend: /home/icarosix/asictoolchain/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
Parsing Verilog input from `/home/icarosix/asictoolchain/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation.
Generating RTLIL representation for module `\$_TBUF_'.
Successfully finished Verilog frontend.

15.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>

16. Executing SIMPLEMAP pass (map simple cells to gate primitives).

17. Executing MUXCOVER pass (mapping to wider MUXes).
here is the repo, the top module is in rtl/ floder and in the lines 109-111 it multiplexes the lines which can be Hi-Z
Have You had similar issues ?
f
@Krzysztof Herman As recent experience has shown you may also need to be careful on hold violations of the resulting clock tree after putting everything together.
k
@FatsieFS Thank You for Your comment, perfect timing because I am facing it right now, I have hold violation. I was thinking to manually modify the GL netlist however I am not sure if it would be the right way
m
I haven't had those issues @Krzysztof Herman
Tristate support isn't great in yosys. I would be careful and very explicit in their use
k
OK, thank You, in fact I have solved the problem, at the level gate level I found the tristate buffers and the problem was in the address decoding
👍 1
Other issue was that the Hi-Z state is generated by the lower hierarchy modules and the top level was not able to synthesize it if (x == 1'bz) seems not to be covered, so I have to generate some extra signal in order to provide the information about Hi-Z. It works!
BTW, You are making great job on Your YT channel, keep going!
👍 1
m
Thanks!
And make sure you do gate level Sims too
We nearly missed the clock buffer issue
k
ok, I will !
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