Krzysztof Herman
10/07/2021, 5:37 PMMatt Venn
10/08/2021, 10:32 AMKrzysztof Herman
10/08/2021, 2:35 PMMatt Venn
10/08/2021, 3:31 PMKrzysztof Herman
10/08/2021, 3:32 PMMatt Venn
10/08/2021, 3:32 PMKrzysztof Herman
10/08/2021, 3:33 PMMatt Venn
10/08/2021, 4:17 PMKrzysztof Herman
10/08/2021, 4:47 PMset ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
Matt Venn
10/08/2021, 5:15 PMTim Edwards
10/08/2021, 5:49 PMverilog/gl/mgmt_protect.v
and the I/O ports are in verilog/gl/gpio_control_block.v
. e.g., data input to the user project from the LA is la_data_in_mprj
(output from mgmt_protect.v
) and the driving cell is a sky130_fd_sc_hd__inv_8
. There are only three pins connected to the user area in gpio_control_block.v
, which are user_gpio_oeb
, user_gpio_out
, and user_gpio_in
, connected to sky130_fd_sc_hd__mux2_1
(load) for the first two, and sky130_fd_sc_hd__einvp_8
(driving) for the last one.Krzysztof Herman
10/08/2021, 6:09 PM15.1. Executing Verilog-2005 frontend: /home/icarosix/asictoolchain/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v
Parsing Verilog input from `/home/icarosix/asictoolchain/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation.
Generating RTLIL representation for module `\$_TBUF_'.
Successfully finished Verilog frontend.
15.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~3 debug messages>
16. Executing SIMPLEMAP pass (map simple cells to gate primitives).
17. Executing MUXCOVER pass (mapping to wider MUXes).
FatsieFS
10/10/2021, 11:34 AMKrzysztof Herman
10/10/2021, 3:18 PMMatt Venn
10/10/2021, 3:40 PMKrzysztof Herman
10/10/2021, 3:41 PMMatt Venn
10/10/2021, 3:45 PMKrzysztof Herman
10/10/2021, 3:47 PM