Matt Venn
10/11/2021, 5:18 PMKrzysztof Herman
10/11/2021, 5:20 PMKrzysztof Herman
10/11/2021, 5:22 PMKrzysztof Herman
10/11/2021, 5:22 PMKrzysztof Herman
10/11/2021, 5:23 PMKrzysztof Herman
10/11/2021, 5:25 PMcic cicmodule( .clk(clk),
.rst(rst),
.we(mclk),
.data_in(pdm_data_i),
.data_out(cic_out)
);
Matt Venn
10/11/2021, 5:25 PMMatt Venn
10/11/2021, 5:25 PMKrzysztof Herman
10/11/2021, 5:28 PMKrzysztof Herman
10/11/2021, 5:39 PMmodule cic #(parameter N = 16)(
input wire clk,
input wire rst,
input wire we,
input wire data_in,
output reg [N-1:0] data_out
);
always@(posedge clk) begin
if(rst)
data_out <= 0;
else if(we)
data_out <= data_out + {{15{1'b0}} , data_in };
end
endmodule
Krzysztof Herman
10/11/2021, 5:39 PMKrzysztof Herman
10/11/2021, 5:40 PMKrzysztof Herman
10/11/2021, 5:54 PMKrzysztof Herman
10/11/2021, 5:56 PM