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# openlane
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Krzysztof Herman
10/15/2021, 1:07 PMHello to all, I have a question about netlist generation for GL simulation using testbench available in caravel_user_project. Do I have to use any special flow settings ? Which netlist shall I use, because in results/synthesis there are a few ones generated at different levels of the flow? Should be the netlist powered ?
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Matt Venn
10/15/2021, 3:57 PMyou should copy your powered lvs netlist to the verilog/gl directory (it might get copied there automatically - not sure)
then you run the test like this: SIM=GL make
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Krzysztof Herman
10/15/2021, 4:36 PMHi @Matt Venn, in fact I am outside the caravel_user_project running a custom design using OpenLane. during the flow I get something like this: merged_unpadded.lef xxx.synthesis_cts.v xxx.synthesis_optimized.v xxx.synthesis_preroute.v xxx.synthesis.v
where xxx is the name of the module I use as top-one
optimized, cts and preroute comes with power pins
which one in Your opinion shall I use
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Matt Venn
10/15/2021, 4:40 PMThe powered lvs one in the results/magic directory
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Krzysztof Herman
10/15/2021, 4:41 PMI found it under results/lvs/ suppose is the same
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I wll estup the simulation and feedback You whether it works or not.
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Matt Venn
10/15/2021, 4:55 PMCheck the /verilog/dv/ examples for the right iverilog arguments
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Krzysztof Herman
10/15/2021, 4:56 PMI use the same makefile
... waiting for the final netlist because I have to synthesize whole project without macros > 60000 cells
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Matt Venn
10/15/2021, 5:08 PMGood luck!
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Krzysztof Herman
10/15/2021, 7:44 PMseems to work
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however looking for the signals in GTKWave is way much hard
once you treat it as a black box all is ok
Once more thank's for Your help!
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