Hello, I have an issue with the gate level simulation results, in general I can view only a few of the registers declared in my datapath even though they are used and work at the RTL level. All that happened when I have multicycled DSP operations. Even the registers that appear do not initialize with a correct value after reset.

can you share your log?

hi

so BLACKBOX option worked?

oo, that was an issue of the @Matt Venn, not mine

check yosys switches for synthesis and use it as per need

yes, I have tried different strategies: DELAY and AREA however without success

sure it isn't the same issues you had before? https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1633973138310600?thread_ts=1633972702.309700&cid=C016H8WJMBR

@Matt Venn I was revising all the datapath looking for possible beaks however until now I could nof find any. The other strange thing s that I have 13 registers declared in the design and some of them are present in the GTKwave and some not. I am even initializing them at reset but without success.

it's so unlikely to be that issue. much more likely that your registers are not being used or initialised correctly

no

read the yosys synth logs, and search for this like optimise or remove

point taken 👍