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Hello, I have an issue with the gate level simulat...
# openlane
k
Hello, I have an issue with the gate level simulation results, in general I can view only a few of the registers declared in my datapath even though they are used and work at the RTL level. All that happened when I have multicycled DSP operations. Even the registers that appear do not initialize with a correct value after reset.
v
can you share your log?
k
hi
in fact all is ok at the RTL and flow level
v
so BLACKBOX option worked?
k
oo, that was an issue of the @Matt Venn, not mine
I have problem with GateLevel simulation
Yosys seems to optimize too much
v
check yosys switches for synthesis and use it as per need
k
yes, I have tried different strategies: DELAY and AREA however without success
m
it's possible yosys has optimised them out in error, but I've never seen it. It's always my fault
k
@Matt Venn I was revising all the datapath looking for possible beaks however until now I could nof find any. The other strange thing s that I have 13 registers declared in the design and some of them are present in the GTKwave and some not. I am even initializing them at reset but without success.
I asw wondering if I should use some special options of synthesis ?
m
it's so unlikely to be that issue. much more likely that your registers are not being used or initialised correctly
try on an fpga?
k
no
look, I have just simulated a version where I commented out all the DSP (filters), yosys gave me like doubled the number of cells, the registers appear and work. I have to revise the DSP block definitely.
m
read the yosys synth logs, and search for this like optimise or remove
that should give you some more clues
k
point taken 👍
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