Channels
hdl21
caravel-documentation
unic-cass-23
events
mpw-6plus-silicon
openchiplets
maker-projects
genius-vlsi
fab-visit
pd-openlane-and-sky130
chipignite2206q_stanford_bringup
courses
magic
activity
align
popy_neel
tinyml
cadence-virtuoso
cryo
tiny-tapeout
maker-zone
pa-test-chip
fossee-iitb-esim
dynamic-power-estimation
rios
ieee-sscs-dc-23
español_vlsi
gfmpw-0-silicon
silicon-validation
fossee-iitb-google-sky130
zettascale
sdram
vhdl
xschem
openroad
openlane
ieee-sscs-dc-22
mpw-one-silicon
mpw-2-silicon
fasoc
team-awesome
japan-region
openfpga
serdes
osu
junk
toysram
cadence-innovus
infiniband
verification-fe
riscv
vhdl-learners
microwatt
digital-design
foss-asic-tools
sram
openpositarithmetic
openadiabaticlogic
openpower
caravan
sky130
tapeout-job
hardware-beginners
aa
design-services
private-shuttle
ieee-sscs-cac
stdcelllib
b2aws
beagleboard
tapeout-pakistan
rad-lab-silicon
timing-closure
piel
announce
skywater
bag
paracells
cadence-spectre
travis-ci
opentitan
strive
openocd
containers
sky65
chisel
radio
neuro-mem
help-
electric
dffram
images
sky90
sky130-ci
swerv
fault
fpga
mpw-one-clean-short
picosoc
layouteditor
researchers
coalition-for-digital-environmental-sustainability
vlsi101
magical
vlsi_verilog_using_opensource_eda
basebands
vlsi_verilog_using_opensoure_eda
cadence-genus
abcc
fuserisc
vliw
openlane_cloudrunner
bluetooth
design-review
digital-electronics-learners
verilog-learners
uvm-learners
mpw-3-silicon
ihp-sg13g2
rdircd
discord-mods
open-microelectronics-textbook
announcements
mwcas-2023-rtl2silicon
gdsfactory
gf180
b2aws-tutorial
gf180mcu
system-verilog-learners
vlsi-learners-group
chilechipmakers
silicon-validation-private
chipignite
vh2v
shuttle-status
board-respin
openhighqualityresonators
venn
xls
rf-mmw-design
nydesign
open-pdk
j-core
power
waveform-viewers
pll
vendor-synopsys
silicon-photonics
lvs
imagesensors
chip-yard
shuttle
adiabatonauts
openram
funding
opendataset-circuitnet-for-ml-tasks-in-vlsi-cad
generative-ai
community_denmark_dtu
open_pdks
lvs-analysis
xyce
shuttle-precheck
openlane-development
efabless
general
analog-design
klayout
caravel-board
reram
ieee-sscs-dc-21q3
sky130-pv-workshop
verification-be
caravel
laygo
openlane-2
jobs
Powered by
#openlane
Title
# openlane
m
Matt Venn
10/26/2021, 10:14 AM
Can we get some help from
@User
or
@User
or
@User
about what to do about timing violations with new openlane? What do we do to solve them?
m
Matt Liberty
10/26/2021, 2:57 PM
@User
can you provide more context to your question? I don't follow all the OL gyrations.
m
Matt Venn
10/26/2021, 2:57 PM
on mpw-3a we are now getting reports of timing violations
image.png
My question is, what are the options we have to solve this?
m
Matt Liberty
10/28/2021, 2:56 PM
A -.02 violation is pretty small. In OL you might try setting PL_RESIZER_SETUP_SLACK_MARGIN or PL_RESIZER_HOLD_SLACK_MARGIN to overfix .
2 Views
Post