Matthew Guthaus
11/12/2021, 1:03 AMSubcircuit summary:
Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__tapvpwrvgnd_1 (1) |sky130_fd_sc_hd__tapvpwrvgnd_1 (1)
sky130_fd_sc_hd__and2_1 (333) |sky130_fd_sc_hd__and2_1 (333)
sky130_fd_sc_hd__and2_2 (38) |sky130_fd_sc_hd__and2_2 (38)
sky130_fd_sc_hd__decap_3 (2917) |sky130_fd_sc_hd__decap_3 (1) **Mismatch**
sky130_fd_sc_hd__clkbuf_2 (227) |sky130_fd_sc_hd__clkbuf_2 (227)
# if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
# ignore class "-circuit2 $cell"
# }
44b715a8 sky130/netgen/sky130_setup.tcl (Mitch Bailey 2020-12-19 21:48:18 +0900 307) # if {[regexp {sky130_fd_sc_[^_]+__decap_[[:digit:]]+} $cell match]} {
44b715a8 sky130/netgen/sky130_setup.tcl (Mitch Bailey 2020-12-19 21:48:18 +0900 308) # ignore class "-circuit1 $cell"
44b715a8 sky130/netgen/sky130_setup.tcl (Mitch Bailey 2020-12-19 21:48:18 +0900 309) # }
but the commit was supposed to IGNORE fill and tap cells
commit 44b715a8cb733069b55d892ebe4786a79b9d5893 (tag: 1.0.91)
Author: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Date: Sat Dec 19 21:48:18 2020 +0900
Ignore fill and tap cells in device level LVS
Mitch Bailey
11/12/2021, 1:44 AMsky130_fd_sc_hd__tapvpwrvgnd_1
cells also being considered during LVS. The sky130A netgen setup file should ignore these too.
Can you post your netgen command?Matthew Guthaus
11/12/2021, 1:48 AMReading netlist file /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/magic/user_project_wrapper.spice
Reading netlist file /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs.powered.v
...
Reading setup file /software/PDKs/sky130A/libs.tech/netgen/sky130A_setup.tcl
Comparison output logged to file /project/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs.lef.log
Logging to file "/project/openlane/user_project_wrapper/runs/user_project_wrapper/results/lvs/user_project_wrapper.lvs.lef.log" enabled
commit 14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad (HEAD, tag: 1.0.234)
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Mon Oct 25 13:18:42 2021 -0400
Updated version to go along with the merge of pull request #169
from Manar Abdelatty.
Mitch Bailey
11/12/2021, 1:56 AMflow.tcl -design user_project_wrapper
?Matthew Guthaus
11/12/2021, 1:57 AMMitch Bailey
11/12/2021, 1:59 AMmpw-3
or mpw-3a
?decap
cells in the user_project_wrapper
LVS log? I'm thinking that it's trying to do a black box compare because I doubt that the spice library is being added to the verilog.Tim Edwards
11/12/2021, 2:03 AMMitch Bailey
11/12/2021, 2:17 AMdecap
cells (I think). Has there been a change to netgen not to parallelize non-empty cells?Tim Edwards
11/12/2021, 2:19 AMMitch Bailey
11/12/2021, 2:25 AMTim Edwards
11/12/2021, 2:27 AMTobias Strauch
11/12/2021, 3:07 PMMatthew Guthaus
11/12/2021, 7:45 PMTobias Strauch
11/13/2021, 8:11 AMMitch Bailey
11/14/2021, 3:36 PMMatthew Guthaus
11/14/2021, 3:45 PMMitch Bailey
11/14/2021, 3:47 PMnetgen -batch
will give you the version.Matthew Guthaus
11/14/2021, 4:12 PM