Hello all, in openlane while running our design, At the lvs check step, flow is getting stuck (not ending) , after running for some time. I am not sure what's the mistake. I checked the generated lvs log file, there weren't any mismatch but it showed two unconnected pins. Can this be a reason for this? if that's the case, what should be done for it? I have attached the lvs log file and lvs report for reference.

Pls post your repo and a screenshot of your placed macro inside user project wrapper with met4 met5 and met4via

@User: This run is not for user_project_wrapper, it is for creating the digital macro to be used in the wrapper. (Similar to user_proj_example)

Ok! So deep in tapeout I'm assuming all issues are related! People are going to find it easier to help if you provide the design files.

@User: I have uploaded my topmost rtl and the generated gate level netlist. I found that, in rtl I have defined only vccd1 and vssd1 as power pins. But in gate level netlist, vccd2 and vssd2 pins are also getting created. Could you help on this?

@User Could it be related to this? https://skywater-pdk.slack.com/archives/C01DZSS46HL/p1636755358071300 You might open the extracted spice netlist and check the ports on the decap cells. They should all be parallel merged, but if there's a port definition problem (like what appears to be fixed by the PR in the link), LVS could be taking a long time.

@User: The issue got cleared. I updated openlane, and deleted my gate level netlist and ran the flow again, then there were no LVS mismatches. Thanks for the support.