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Matt Venn

11/17/2021, 4:17 PM
I thought ROMs were done with standard cells for 1s and 0s, but I've just done some experiements and it seems that yosys is synthesising logic that gives the same output as a ROM. Is that expected?
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Matthew Guthaus

11/17/2021, 5:40 PM
Yes that is expected. You mean tie high and low cells?
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Matt Venn

11/17/2021, 5:41 PM
Yes
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Matthew Guthaus

11/17/2021, 5:41 PM
Yosys will try to avoid using those in general. It can propagate the logic and minimize things.