https://open-source-silicon.dev logo
#openlane
Title
# openlane
h

Hieu Bui

11/23/2021, 10:14 AM
The PDN scripts in OpenLane seem broken when using multiple power domains. It can connect only vccd1 and vssd1. I am trying to re-submit our design (with timing errors) from the MPW-2 but the PDN scripts in openlane can't connect the hard macro to vccd2 and vssd2. Do you know any workaround to bypass this? I got this warning: "[WARNING]: All internal macros will not be connected to power." and the power net are not connected". This is my config:
Copy code
set ::env(FP_PDN_MACRO_HOOKS) "vco_adc_wrapper_1 vccd1 vssd1, vco_0 vccd2 vssd2, vco_1 vccd2 vssd2, vco_2 vccd2 vssd2"
set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
 set ::env(FP_PDN_CHECK_NODES) 0

set ::env(VDD_NETS) [list {vccd1} {vccd2} {vdda1} {vdda2}]
set ::env(GND_NETS) [list {vssd1} {vssd2} {vssa1} {vssa2}]
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(FP_PDN_ENABLE_RAILS) 0
👍 2
r

Rahul Bharadwaj

11/24/2021, 5:16 AM
Hello @User Is this issue resolved?
h

Hieu Bui

11/24/2021, 5:32 AM
I tried to change the code but it seems that it makes no effect. I still have the issue.
r

Rahul Bharadwaj

11/24/2021, 5:33 AM
ohh ok.
@User I saw your project for chipignite where you have succeeded the precheck so is this issue solved?
h

Hieu Bui

11/27/2021, 5:48 AM
I temporarily connect our analog module to vccd1 and vssd1 because it also uses 1.8V supply. The problem haven't been solved yet.
r

Rahul Bharadwaj

11/27/2021, 5:48 AM
Ok @User thanks.