Hi I m habing an issue with the systhesis with openlane With

Question

Hi I m habing an issue with the systhesis with openlane With the example works fine but when I try my project I have and error ERROR CTS 0056 Error when finding clk nets in DB I tested the design in a FPGA and works anyone can point me on were I need look in the reports to see why is failing

Wajeh ul hasan · Answer

Check if the config tcl has clock defined same as your design

Ivan Rodriguez · Answer

yes I check that in both the json and the tlc

Matthew Guthaus · Answer

< U021AUA76NS> the json is ignored if there is a tcl Can you provide an example The clock net is used for CTS but the clock port is used for STA

Matthew Guthaus · Answer

You can look in the early synthesis reports The exact ones depends on your options

Ivan Rodriguez · Answer

set max fanout 5 0000 current design INFO Setting RC values INFO Configuring cts characterization INFO Performing clock tree synthesis INFO Looking for the following net s main module clk INFO Running Clock Tree Synthesis ERROR CTS 0056 Error when finding clk nets in DB Error or cts tcl 57 CTS 0056

Ivan Rodriguez · Answer

this is the full error log

Matthew Guthaus · Answer

Your design would help too Can you just point to a repo

Ivan Rodriguez · Answer

This is how is implemented in the user example

Ivan Rodriguez · Answer

Ivan Rodriguez · Answer

sure this is the repo

Matthew Guthaus · Answer

It is a little confusing because your instance and module are both main module I m not sure if that matters

Matthew Guthaus · Answer

The repo is using the default clock set env CLOCK NET mprj clk

Ivan Rodriguez · Answer

that setting is in the caravel part Is needed to change that

Ivan Rodriguez · Answer

It is a little confusing because your instance and module are both main module I m not sure if that matters For this in the MPW 2 I have the same name and not issue I don t know if now affects I will try

Matthew Guthaus · Answer

The clock net in your configuration will be relative to the top of user project wrapper as far as I know

Matthew Guthaus · Answer

Since you are synthesizing that

Matthew Guthaus · Answer

Caravel has its own config that you don t need to change since you aren t synthesizing it

Matthew Guthaus · Answer

Ivan Rodriguez · Answer

I m changing that to test But I m doing the hardening of the user proj example

Ivan Rodriguez · Answer

I change the net of the wrapper but same result I tested one thing I take the example and remove some of the outputs and only removing some outputs in this case the counter one And I get a similar error

Ivan Rodriguez · Answer

so I don t know if is a simplification from yosys and for that the net is not found

Ivan Rodriguez · Answer

Error or cts tcl 57 CTS 0056 In the error line there is this line or cts tcl is a file in openlane and the line 57 is this sink clustering max diameter $ env CTS SINK CLUSTERING MAX DIAMETER

Ivan Rodriguez · Answer

is not that

Matthew Guthaus · Answer

Yes I ve run into this before If you specify an internal net it may go away if yosys does some buffering of it using its non clock fanout optization Can you just specify clk in the top level rather than main module clk

Ivan Rodriguez · Answer

yes I try that and same error

Ivan Rodriguez · Answer

I try this set env CLOCK PORT wb clk i set env CLOCK NET wb clk i

Ivan Rodriguez · Answer

and that manage to work but I don t know is is correct

Matt Liberty · Answer

cts is called with clk nets $ env CLOCK NET so CLOCK NET must be the name of a valid net It would be simpler if the clock is in the SDC and that line were just omitted

Matt Liberty · Answer

Matthew Guthaus · Answer

The one difference is that STA requires a port not a net

Matthew Guthaus · Answer

Slightly different

Ivan Rodriguez · Answer

so is correct that the net and the port is the same this is correct or will cause some issues

Matthew Guthaus · Answer

They can be the same but they call also be different For example if you want to gate the clock in a module with an enable you should specify the net after the gate but sta will need the net at the input because that is a port At least that is my understanding from when I played with it to get my design to work

Ivan Rodriguez · Answer

now I continue the openlane process and I get this error

Ivan Rodriguez · Answer

ERROR during executing openroad exit openlane scripts openroad or resizer routing timing tcl | amp tee gt amp stdout project openlane user proj example runs user proj example logs routing 15 resizer timing optimization log ERROR Exit code 1 ERROR Last 10 lines child killed segmentation violation

Ivan Rodriguez · Answer

so I don t know if is related to the clock net

Matt Liberty · Answer

with any case you should file a GH issue with a test case

Ivan Rodriguez · Answer

I think that I found the issue but not the solution The problem is in the openlane file user proj example synthesis v the main module clk does not appear When I try the caravel user project example the wire conunter clk appear So definitely is some kind of optimization that eliminates the net

Matthew Guthaus · Answer

I m the counter example it likely isn t such a high fan out net so yosys probably doesn t do as much Can you tell yosys to not touch it

Ivan Rodriguez · Answer

Can you tell yosys to not touch it how I do that I m new to these synthesis tools

Matthew Guthaus · Answer

I don t know in yosys

Matthew Guthaus · Answer