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#openlane
Title
# openlane
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Mitch Bailey

02/02/2022, 2:24 AM
This may be a question for #openroad, but it seems that unused io signals are synthesized as connections to ground. For example, in this rtl, the output signals
io_out
are unused. In the resulting gate level verilog, these signals have all been tied to ground.
Copy code
sky130_fd_sc_hd__conb_1 _60713_ (.LO(io_out[0]),
    .VGND(vssd1),
    .VNB(vssd1),
    .VPB(vccd1),
    .VPWR(vccd1));
This can lead to unexpected results, if "unused" signals are shared with actual signals from other modules. Is this a yosys issue? @User
🌍 1
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Matt Liberty

02/02/2022, 4:10 AM
those all look like power pins so I'm not clear what the issue is
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Mitch Bailey

02/02/2022, 4:37 AM
Copy code
.LO(io_out[0])
a

Arman Avetisyan

02/02/2022, 10:07 AM
Known bug
Issue 878 in openlane
I debugged it, it seems to be coming from yosys scripts or bug. Didnt debug further, I still have other issues to fix
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Matt Liberty

02/02/2022, 12:31 PM
Sorry I missed it was a tie cell. This looks to be a known yosys issue https://github.com/YosysHQ/yosys/issues/511