This may be a question for <#C0161A4A59V|openroad>...
# openlane
This may be a question for #openroad, but it seems that unused io signals are synthesized as connections to ground. For example, in this rtl, the output signals
are unused. In the resulting gate level verilog, these signals have all been tied to ground.
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sky130_fd_sc_hd__conb_1 _60713_ (.LO(io_out[0]),
This can lead to unexpected results, if "unused" signals are shared with actual signals from other modules. Is this a yosys issue? @User
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those all look like power pins so I'm not clear what the issue is
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Known bug
Issue 878 in openlane
I debugged it, it seems to be coming from yosys scripts or bug. Didnt debug further, I still have other issues to fix
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Sorry I missed it was a tie cell. This looks to be a known yosys issue