This may be a question for #openroad, but it seems that unused io signals are synthesized as connections to ground. For example, in this rtl, the output signals

io_out

are unused. In the resulting gate level verilog, these signals have all been tied to ground.

sky130_fd_sc_hd__conb_1 _60713_ (.LO(io_out[0]),
    .VGND(vssd1),
    .VNB(vssd1),
    .VPB(vccd1),
    .VPWR(vccd1));

This can lead to unexpected results, if "unused" signals are shared with actual signals from other modules. Is this a yosys issue? @User

those all look like power pins so I'm not clear what the issue is

Known bug

Sorry I missed it was a tie cell. This looks to be a known yosys issue https://github.com/YosysHQ/yosys/issues/511