open-source-silicon.dev

This may be a question for <#C0161A4A59V|openroad>, but it seems that unused io signals are synthesized as connections to ground.
For example, in this <https://github.com/ISL-ECE-CEG-AU/GPS_Baseband/blob/main/verilog/rtl/user_proj_example.v|rtl>, the output signals `io_out` are unused.
In the resulting <https://github.com/ISL-ECE-CEG-AU/GPS_Baseband/blob/main/verilog/gl/user_proj_example.v|gate level verilog>, these signals have all been tied to ground.
``` sky130_fd_sc_hd__conb_1 _60713_ (.LO(io_out[0]),
    .VGND(vssd1),
    .VNB(vssd1),
    .VPB(vccd1),
    .VPWR(vccd1));```
This can lead to unexpected results, if "unused" signals are shared with actual signals from other modules. Is this a yosys issue?
<@U01RSNFAM55>

those all look like power pins so I'm not clear what the issue is

I debugged it, it seems to be coming from yosys scripts or bug. Didnt debug further, I still have other issues to fix

Sorry I missed it was a tie cell.  This looks to be a known yosys issue <https://github.com/YosysHQ/yosys/issues/511>