hi i had some hold violations that were resolved by increasi

Question

hi i had some hold violations that were resolved by increasing `PL RESIZER HOLD SLACK MARGIN` but now i m trying to learn to interpret the timing report and I see all clock network delays are zero see thread does this indicate that i have something misconfigured and the clock delays aren t getting modeled properly in the timing analysis

andrew foote · Answer

snippet from reports routing 26 parasitics sta min rpt ```=========================================================================== report checks path delay min Hold ============================================================================ Startpoint wb data i 4 input port clocked by wb clock i Endpoint 22900 rising edge triggered flip flop clocked by wb clock i Path Group wb clock i Path Type min Fanout Cap Slew Delay Time Description 0 00 0 00 clock wb clock i rise edge 0 00 0 00 clock network delay propagated 2 00 2 00 v input external delay 0 03 0 02 2 02 v wb data i 4 in 2 0 01 wb data i 4 net 0 03 0 00 2 02 v hold79 A sky130 fd sc hd clkdlybuf4s50 1 0 10 0 44 2 46 v hold79 X sky130 fd sc hd clkdlybuf4s50 1 1 0 01 net341 net 0 10 0 00 2 46 v input16 A sky130 fd sc hd buf 12 0 02 0 14 2 60 v input16 X sky130 fd sc hd buf 12 1 0 01 net16 net 0 02 0 00 2 60 v hold78 A sky130 fd sc hd buf 12 0 09 0 15 2 74 v hold78 X sky130 fd sc hd buf 12 8 0 17 net340 net 0 10 0 02 2 77 v 15792 A sky130 fd sc hd buf 8 0 08 0 18 2 95 v 15792 X sky130 fd sc hd buf 8 10 0 10 03298 net 0 08 0 01 2 96 v 16441 A sky130 fd sc hd buf 2 0 07 0 17 3 13 v 16441 X sky130 fd sc hd buf 2 5 0 03 03699 net 0 07 0 00 3 13 v 16759 A sky130 fd sc hd clkbuf 2 0 08 0 15 3 28 v 16759 X sky130 fd sc hd clkbuf 2 5 0 02 03893 net 0 08 0 00 3 28 v 16837 A0 sky130 fd sc hd mux2 1 0 05 0 28 3 56 v 16837 X sky130 fd sc hd mux2 1 1 0 00 03939 net 0 05 0 00 3 56 v 16838 A sky130 fd sc hd clkbuf 1 0 02 0 08 3 64 v 16838 X sky130 fd sc hd clkbuf 1 1 0 00 01026 net 0 02 0 00 3 64 v 22900 D sky130 fd sc hd dfxtp 2 3 64 data arrival time 0 00 0 00 clock wb clock i rise edge 0 00 0 00 clock source latency 0 53 0 39 0 39 ^ wb clock i in 2 0 12 wb clock i net 0 53 0 00 0 39 ^ clkbuf 0 wb clock i A sky130 fd sc hd clkbuf 16 0 06 0 27 0 65 ^ clkbuf 0 wb clock i X sky130 fd sc hd clkbuf 16 4 0 03 clknet 0 wb clock i net 0 06 0 00 0 66 ^ clkbuf 1 1 0 wb clock i A sky130 fd sc hd clkbuf 2 0 09 0 15 0 81 ^ clkbuf 1 1 0 wb clock i X sky130 fd sc hd clkbuf 2 1 0 02 clknet 1 1 0 wb clock i net 0 09 0 00 0 81 ^ clkbuf 1 1 1 wb clock i A sky130 fd sc hd clkbuf 2 0 27 0 29 1 10 ^ clkbuf 1 1 1 wb clock i X sky130 fd sc hd clkbuf 2 4 0 05 clknet 1 1 1 wb clock i net 0 27 0 00 1 10 ^ clkbuf 2 2 0 wb clock i A sky130 fd sc hd clkbuf 2 0 07 0 20 1 30 ^ clkbuf 2 2 0 wb clock i X sky130 fd sc hd clkbuf 2 1 0 01 clknet 2 2 0 wb clock i net 0 07 0 00 1 30 ^ clkbuf 2 2 1 wb clock i A sky130 fd sc hd clkbuf 2 0 27 0 28 1 59 ^ clkbuf 2 2 1 wb clock i X sky130 fd sc hd clkbuf 2 4 0 05 clknet 2 2 1 wb clock i net 0 27 0 00 1 59 ^ clkbuf 3 5 0 wb clock i A sky130 fd sc hd clkbuf 2 0 20 0 29 1 89 ^ clkbuf 3 5 0 wb clock i X sky130 fd sc hd clkbuf 2 4 0 04 clknet 3 5 0 wb clock i net 0 20 0 00 1 89 ^ clkbuf 4 10 0 wb clock i A sky130 fd sc hd clkbuf 2 0 17 0 25 2 14 ^ clkbuf 4 10 0 wb clock i X sky130 fd sc hd clkbuf 2 4 0 03 clknet 4 10 0 wb clock i net 0 17 0 00 2 14 ^ clkbuf 5 21 0 wb clock i A sky130 fd sc hd clkbuf 2 0 12 0 21 2 35 ^ clkbuf 5 21 0 wb clock i X sky130 fd sc hd clkbuf 2 4 0 02 clknet 5 21 0 wb clock i net 0 12 0 00 2 35 ^ clkbuf 6 43 0 wb clock i A sky130 fd sc hd clkbuf 2 0 74 0 64 2 99 ^ clkbuf 6 43 0 wb clock i X sky130 fd sc hd clkbuf 2 20 0 14 clknet 6 43 0 wb clock i net 0 74 0 01 3 00 ^ clkbuf leaf 341 wb clock i A sky130 fd sc hd clkbuf 16 0 07 0 30 3 30 ^ clkbuf leaf 341 wb clock i X sky130 fd sc hd clkbuf 16 11 0 04 clknet leaf 341 wb clock i net 0 07 0 00 3 30 ^ 22900 CLK sky130 fd sc hd dfxtp 2 0 25 3 55 clock uncertainty 0 00 3 55 clock reconvergence pessimism 0 03 3 52 library hold time 3 52 data required time 3 52 data required time 3 64 data arrival time 0 12 slack MET ```

Arman Avetisyan · Answer

1 its reports for hold min delay 2 The network delay is clearly shown see the hold fixing buffers etc The propogated clock delay is I would assume a constraint not the actual network delay

andrew foote · Answer

thanks the report above is just one example i see the same for all paths min amp max i did see that there s a lot buffers amp delays that are accounted for in the path just a bit confused about the clock network delay row and how that relates

Arman Avetisyan · Answer

It s Input to register timing path There is no launch clock delay since it s an input with delay set by constaints