hi - i had some hold violations that were resolved...
# openlane
a
hi - i had some hold violations that were resolved by increasing
PL_RESIZER_HOLD_SLACK_MARGIN
, but now i'm trying to learn to interpret the timing report, and I see all clock network delays are zero (see thread). does this indicate that i have something misconfigured and the clock delays aren't getting modeled properly in the timing analysis?
snippet from reports/routing/26-parasitics_sta.min.rpt:
Copy code
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: wb_data_i[4] (input port clocked by wb_clock_i)
Endpoint: _22900_ (rising edge-triggered flip-flop clocked by wb_clock_i)
Path Group: wb_clock_i
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock wb_clock_i (rise edge)
                          0.00    0.00   clock network delay (propagated)
                          2.00    2.00 v input external delay
                  0.03    0.02    2.02 v wb_data_i[4] (in)
     2    0.01                           wb_data_i[4] (net)
                  0.03    0.00    2.02 v hold79/A (sky130_fd_sc_hd__clkdlybuf4s50_1)
                  0.10    0.44    2.46 v hold79/X (sky130_fd_sc_hd__clkdlybuf4s50_1)
     1    0.01                           net341 (net)
                  0.10    0.00    2.46 v input16/A (sky130_fd_sc_hd__buf_12)
                  0.02    0.14    2.60 v input16/X (sky130_fd_sc_hd__buf_12)
     1    0.01                           net16 (net)
                  0.02    0.00    2.60 v hold78/A (sky130_fd_sc_hd__buf_12)
                  0.09    0.15    2.74 v hold78/X (sky130_fd_sc_hd__buf_12)
     8    0.17                           net340 (net)
                  0.10    0.02    2.77 v _15792_/A (sky130_fd_sc_hd__buf_8)
                  0.08    0.18    2.95 v _15792_/X (sky130_fd_sc_hd__buf_8)
    10    0.10                           _03298_ (net)
                  0.08    0.01    2.96 v _16441_/A (sky130_fd_sc_hd__buf_2)
                  0.07    0.17    3.13 v _16441_/X (sky130_fd_sc_hd__buf_2)
     5    0.03                           _03699_ (net)
                  0.07    0.00    3.13 v _16759_/A (sky130_fd_sc_hd__clkbuf_2)
                  0.08    0.15    3.28 v _16759_/X (sky130_fd_sc_hd__clkbuf_2)
     5    0.02                           _03893_ (net)
                  0.08    0.00    3.28 v _16837_/A0 (sky130_fd_sc_hd__mux2_1)
                  0.05    0.28    3.56 v _16837_/X (sky130_fd_sc_hd__mux2_1)
     1    0.00                           _03939_ (net)
                  0.05    0.00    3.56 v _16838_/A (sky130_fd_sc_hd__clkbuf_1)
                  0.02    0.08    3.64 v _16838_/X (sky130_fd_sc_hd__clkbuf_1)
     1    0.00                           _01026_ (net)
                  0.02    0.00    3.64 v _22900_/D (sky130_fd_sc_hd__dfxtp_2)
                                  3.64   data arrival time

                          0.00    0.00   clock wb_clock_i (rise edge)
                          0.00    0.00   clock source latency
                  0.53    0.39    0.39 ^ wb_clock_i (in)
     2    0.12                           wb_clock_i (net)
                  0.53    0.00    0.39 ^ clkbuf_0_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_16)
                  0.06    0.27    0.65 ^ clkbuf_0_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_16)
     4    0.03                           clknet_0_wb_clock_i (net)
                  0.06    0.00    0.66 ^ clkbuf_1_1_0_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_2)
                  0.09    0.15    0.81 ^ clkbuf_1_1_0_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_2)
     1    0.02                           clknet_1_1_0_wb_clock_i (net)
                  0.09    0.00    0.81 ^ clkbuf_1_1_1_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_2)
                  0.27    0.29    1.10 ^ clkbuf_1_1_1_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_2)
     4    0.05                           clknet_1_1_1_wb_clock_i (net)
                  0.27    0.00    1.10 ^ clkbuf_2_2_0_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_2)
                  0.07    0.20    1.30 ^ clkbuf_2_2_0_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_2)
     1    0.01                           clknet_2_2_0_wb_clock_i (net)
                  0.07    0.00    1.30 ^ clkbuf_2_2_1_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_2)
                  0.27    0.28    1.59 ^ clkbuf_2_2_1_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_2)
     4    0.05                           clknet_2_2_1_wb_clock_i (net)
                  0.27    0.00    1.59 ^ clkbuf_3_5_0_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_2)
                  0.20    0.29    1.89 ^ clkbuf_3_5_0_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_2)
     4    0.04                           clknet_3_5_0_wb_clock_i (net)
                  0.20    0.00    1.89 ^ clkbuf_4_10_0_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_2)
                  0.17    0.25    2.14 ^ clkbuf_4_10_0_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_2)
     4    0.03                           clknet_4_10_0_wb_clock_i (net)
                  0.17    0.00    2.14 ^ clkbuf_5_21_0_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_2)
                  0.12    0.21    2.35 ^ clkbuf_5_21_0_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_2)
     4    0.02                           clknet_5_21_0_wb_clock_i (net)
                  0.12    0.00    2.35 ^ clkbuf_6_43_0_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_2)
                  0.74    0.64    2.99 ^ clkbuf_6_43_0_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_2)
    20    0.14                           clknet_6_43_0_wb_clock_i (net)
                  0.74    0.01    3.00 ^ clkbuf_leaf_341_wb_clock_i/A (sky130_fd_sc_hd__clkbuf_16)
                  0.07    0.30    3.30 ^ clkbuf_leaf_341_wb_clock_i/X (sky130_fd_sc_hd__clkbuf_16)
    11    0.04                           clknet_leaf_341_wb_clock_i (net)
                  0.07    0.00    3.30 ^ _22900_/CLK (sky130_fd_sc_hd__dfxtp_2)
                          0.25    3.55   clock uncertainty
                          0.00    3.55   clock reconvergence pessimism
                         -0.03    3.52   library hold time
                                  3.52   data required time
-----------------------------------------------------------------------------
                                  3.52   data required time
                                 -3.64   data arrival time
-----------------------------------------------------------------------------
                                  0.12   slack (MET)
a
1. its reports for hold (min delay) 2. The network delay is clearly shown, see the hold fixing buffers, etc. The propogated clock delay is I would assume a constraint, not the actual network delay
a
thanks! the report above is just one example, i see the same for all paths (min & max). i did see that there's a lot buffers & delays that are accounted for in the path, just a bit confused about the 'clock network delay' row and how that relates.
a
It's Input to register timing path. There is no launch clock delay, since it's an input with delay set by constaints