Hi, I am running openlane to make my updated <user...
# openlane
Hi, I am running openlane to make my updated user_project_wrapper.v around a small blackboxed module (col_driver.v), but running into LVS errors on LEF. Going by this discussion (https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1647191149832239?thread_ts=1646668982.224529&amp;cid=C016H8WJMBR), I pulled up my 30-user_project_wrapper.lef.log and see some confusion around power pins:
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Subcircuit pins:
Circuit 1: user_project_wrapper            |Circuit 2: user_project_wrapper            
analog_io[3]                               |analog_io[3]                               
(no matching pin)                          |vccd1                                      
(no matching pin)                          |vssd1                                      
vccd1                                      |(no matching pin)                          
vssd1                                      |(no matching pin)
Why are power pins showing as having no matches? I am copying the same ifdef structure for defining power pins as in the counter example… Any help would be appreciated! cc: @User @User
@User From the list of disconnected nets, it looks like the power isn't being connected in the gate level verilog. Can you post the gate level versions of your netlists (as opposed to the rtl version)?
Oh I am missing a step then…I don’t have a gate level netlist! I am trying to wrap a custom layout (in magic) into caravel’s user_project_wrapper. I assumed that I could just make a dummy verilog file with the same ports as the gds exported from magic, and instance that into the wrapper verilog for calling openlane. I can try to extract a netlist from magic though — would that be considered gate level (it would just be switches and reram cells).
I tried making a skeletal gate-level netlist: user_project_wrapper.v but I still get the same LVS error where the supply pins don’t match.
Why do they not match? Are the connected? how did you confugre it to connect?
That’s what’s confusing me…but maybe I am comparing the wrong verilog files. Looking at 30-lef.log, netgen failed LVS comparing user_project_wrapper.spice with 27-powered_netlist.v The extracted spice file has:
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.subckt user_project_wrapper analog_io[0] analog_io[10] analog_io[11] analog_io[12]
+ user_irq[1] user_irq[2] vccd1 vccd2 vdda1 vdda2 vssa1 vssa2 vssd1 vssd2 wb_clk_i
and the powered verilog netlist has:
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module user_project_wrapper (user_clock2,
Port will exist regardless. What are the connections that are failing.
Sorry I don’t follow — how do I find out if I have failing connections in LVS? I couldn’t figure that out from the log https://github.com/3x10e8/ReRAM-16x16/blob/design/openlane/user_project_wrapper/runs/user_project_wrapper/logs/finishing/30-lef.log
From your
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Xcol_driver_west analog_io[3] analog_io[5] analog_io[0] io_in[2] io_in[1] io_in[0]
+ analog_io[4] analog_io[1] col_driver_west/vssd1 col_driver_west/vccd1 col_driver
You can see that the
power is not connected to the
❤️ 1
You might see more detail in
Oh is the problem that the Xcol_… instance of col_driver labelling the pins as col_driver_west/vssd1 and not straight up vssd1?
I was running into a problem with routing the power domains. I am also using openlane (config.tcl) to make an updated user_project_wrapper.v around a blackboxed module top.v. The error log shows it can’t find vdda1 and vccd1 power domains when executing groute.tcl script
The openlane.log file from make user_project_wrapper if it helps! @User
Have you set
I set the following in config.tcl for user_project_wrapper — set ::env(FP_PDN_MACRO_HOOKS) “\ top_module vdda1 vccd1 vssd1”
top_module was the instance name for top.v in user_project_wrapper.v
I added a second ground in set ::env(FP-PDN_MACRO_HOOKS) “\top_module vdda1 vssa1 vccd1 vssd1” which fixed the power supply error but the other error message still shows up - ‘error during executing openroad script /openlane/scripts/openroad/groute.tcl’
The openlane log showed a message ‘routing congestion too high’ just before this error as well
These are probably the variables that you need to check.
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FP_PDN_ENABLE_MACROS_GRID	Enables the connection of macros to the top level power grid. 0=Disable 1=Enable.
(Default: 1)

FP_PDN_MACRO_HOOKS	Specifies explicit power connections of internal macros to the top level power grid. Comma separated list of macro instance names and power domain vdd and ground net names: <instance_name> <vdd_net> <gnd_net>
(Default: macros are connected to the first power domain)

FP_PDN_CHECK_NODES	Enables checking for unconnected nodes in the power grid. 0=Disable 1=Enable.
(Default: 1)
Looks like you're trying to connect 2 vdd nets and one two gnd nets to your top_module. I don't know if that's possible with the current flow.
Thank you for the help @User! Do you recommend other ways to have two power domains in my top module?
I think
has multiple domains. Maybe you can use that as a reference, but I have no actual experience.