does anyone know if yosys can synthesise scan flop...
# openlane
a
does anyone know if yosys can synthesise scan flops for scan chains?
t
That's not a synthesis step---it's a special process like adding in a clock tree or input/output buffers. You need a system to replace the flops with scan flops, wire them together post-placement in the most efficient way possible, and then insert delays as necessary to keep the scan chain from having hold violations. There is one system to do that here: https://github.com/Cloud-V/Fault
Note that "fault" was written and is maintained by the same people that brought you "Openlane". Mostly it's the work of Manar Abdelnatty, under the tutelage of Mohamed Shalan.
a
thanks for the tip
but i think this is also a synthesis problem: scan flops include (at least in sky130) include an enable signal and mux to select scan data (an additional pin). in my experiments yosys otherwise infers this same mux separately. the buffer insertion problem to avoid hold time violation is generally there too, isn't it?
in any case, cadence genus will synthesise & map to scan flops but yosys will not
obviously a separate process can compensate for this; i guess that's what fault does. i'll have a look
ah no fault does a lot more than this
my very precise need is to synthesise and map a scan chain with scan flops instead of regular flops. i do not need a full test structure 😞
r
@User did you try the whole flow as mentioned in read.me file?
I am facing this issue
a
@User no, i don't think fault does what i want
it seems that Fault is designed to implement scan chains in existing designs to add test harnesses to those designs, etc
i'm trying to compare the proprietary flow (cadence) to yosys outputs. the design is just a small memory and a decoder. the memory is a scan chain. yosys will infer regular flops + muxes to implement the scan flop functionality, cadence just infers a scan flop in place. the cadence solution is less than half as many cells
correct me if i'm wrong, but it doesn't seem like Fault is going to fix that synthesis step, it just going to add scan chains in place of existing flip flops, which is redundant in this case
r
Yes, You are correct. Fault is designed to implement only scan chain and I also did one experiment yosys vs genus. Genus provide very optimized result
@User can you help me? I am facing this issue
d
I'll take a look at the issue- just extremely busy at the moment
1
a
I talked to eddie hung and he suggested that the yosys 'pattern matcher' tools would be good for identifying the mux + dff combos that can be turned into scan flops. So the answer is that yosys can do it with some work
1
r
Thanks @User for sharing the information