does anyone know if yosys can synthesise scan flops for scan

Question

does anyone know if yosys can synthesise scan flops for scan chains

Tim Edwards · Answer

That s not a synthesis step it s a special process like adding in a clock tree or input output buffers You need a system to replace the flops with scan flops wire them together post placement in the most efficient way possible and then insert delays as necessary to keep the scan chain from having hold violations There is one system to do that here <https github com Cloud V Fault>

Tim Edwards · Answer

Note that fault was written and is maintained by the same people that brought you Openlane Mostly it s the work of Manar Abdelnatty under the tutelage of Mohamed Shalan

aryap · Answer

thanks for the tip

aryap · Answer

but i think this is also a synthesis problem scan flops include at least in sky130 include an enable signal and mux to select scan data an additional pin in my experiments yosys otherwise infers this same mux separately the buffer insertion problem to avoid hold time violation is generally there too isn t it

aryap · Answer

in any case cadence genus will synthesise amp map to scan flops but yosys will not

aryap · Answer

obviously a separate process can compensate for this i guess that s what fault does i ll have a look

aryap · Answer

ah no fault does a lot more than this

aryap · Answer

my very precise need is to synthesise and map a scan chain with scan flops instead of regular flops i do not need a full test structure disappointed

Rameen Anwar · Answer

< U01837QU37V> did you try the whole flow as mentioned in file

Rameen Anwar · Answer

I am facing <https github com Cloud V Fault issues 25|this> issue

aryap · Answer

< U021XG0KXU5> no i don t think fault does what i want

aryap · Answer

it seems that Fault is designed to implement scan chains in existing designs to add test harnesses to those designs etc

aryap · Answer

i m trying to compare the proprietary flow cadence to yosys outputs the design is just a small memory and a decoder the memory is a scan chain yosys will infer regular flops + muxes to implement the scan flop functionality cadence just infers a scan flop in place the cadence solution is less than half as many cells

aryap · Answer

correct me if i m wrong but it doesn t seem like Fault is going to fix that synthesis step it just going to add scan chains in place of existing flip flops which is redundant in this case

Rameen Anwar · Answer

Yes You are correct Fault is designed to implement only scan chain and I also did one experiment yosys vs genus Genus provide very optimized result

Rameen Anwar · Answer

< U020J2W6Q84> can you help me I am facing issue

donn · Answer

I ll take a look at the issue just extremely busy at the moment

aryap · Answer

I talked to eddie hung and he suggested that the yosys pattern matcher tools would be good for identifying the mux + dff combos that can be turned into scan flops So the answer is that yosys can do it with some work

Rameen Anwar · Answer

Thanks < U01837QU37V> for sharing the information