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Binoy B

04/13/2022, 5:40 AM
How to call openlane from terminal and convert verilog file into GDS. I don't mean the way to convert user project into GDS, but any verilog file to GDS after invoking openlane from terminal?
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Vijayan Krishnan

04/13/2022, 5:45 AM
If you followed this https://github.com/The-OpenROAD-Project/OpenLane#prerequisites and installed OpenLane mean, Just do
Copy code
cd OpenLane
make mount
./flow.tcl -design <desgin-name>
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Examples refer OpenLane/designs/spm
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Binoy B

04/13/2022, 6:05 AM
Is there any way to call sram cell in verilog other than using the conventional way of making ram array in verilog?
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Vijayan Krishnan

04/13/2022, 8:27 AM
sram_macros you can find inside part of pdks
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Binoy B

04/13/2022, 8:29 AM
Is there a way to specify sram macro in verilog?
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Vijayan Krishnan

04/13/2022, 9:19 AM
Just export port connection to top module by instantiating sram macro. Refer fakeram macros.v here https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/nangate45/bp_fe_top/macros.v
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