How to call openlane from terminal and convert verilog file into GDS. I don't mean the way to convert user project into GDS, but any verilog file to GDS after invoking openlane from terminal?

If you followed this https://github.com/The-OpenROAD-Project/OpenLane#prerequisites and installed OpenLane mean, Just do

cd OpenLane
make mount
./flow.tcl -design <desgin-name>

Is there any way to call sram cell in verilog other than using the conventional way of making ram array in verilog?

sram_macros you can find inside part of pdks

Is there a way to specify sram macro in verilog?

Just export port connection to top module by instantiating sram macro. Refer fakeram macros.v here https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/nangate45/bp_fe_top/macros.v