From quickstart rst when I ran make module name I got an err open-source-silicon #openlane

Channels

caravel-documentation

mpw-6plus-silicon

pd-openlane-and-sky130

chipignite2206q_stanford_bringup

cadence-virtuoso

fossee-iitb-esim

dynamic-power-estimation

ieee-sscs-dc-23

gfmpw-0-silicon

silicon-validation

fossee-iitb-google-sky130

ieee-sscs-dc-22

mpw-one-silicon

cadence-innovus

verification-fe

foss-asic-tools

openpositarithmetic

openadiabaticlogic

hardware-beginners

design-services

private-shuttle

tapeout-pakistan

rad-lab-silicon

cadence-spectre

mpw-one-clean-short

coalition-for-digital-environmental-sustainability

vlsi_verilog_using_opensource_eda

vlsi_verilog_using_opensoure_eda

openlane_cloudrunner

digital-electronics-learners

verilog-learners

open-microelectronics-textbook

mwcas-2023-rtl2silicon

system-verilog-learners

vlsi-learners-group

chilechipmakers

silicon-validation-private

openhighqualityresonators

waveform-viewers

vendor-synopsys

silicon-photonics

opendataset-circuitnet-for-ml-tasks-in-vlsi-cad

community_denmark_dtu

shuttle-precheck

openlane-development

ieee-sscs-dc-21q3

sky130-pv-workshop

verification-be

Title

# openlane

u

ufuk

05/09/2022, 7:54 PM

From quickstart.rst, when I ran "make module_name" I got an error below. What is wrong here?

m

Mitch Bailey

05/09/2022, 10:46 PM

Do you have a directory

openlane/AES_top_wb

that contains

config.tcl

?