https://open-source-silicon.dev logo
#openlane
Title
# openlane
a

aryap

05/13/2022, 9:39 PM
is there an easy way to pass Verilog `define`s through the openlane flow to yosys for synthesis?
m

Matt Venn

05/14/2022, 6:55 AM
Yes cant remember exactly but search synth in the openlane options
🙏 1
a

aryap

05/14/2022, 5:05 PM
thanks matt
m

Matt Venn

05/14/2022, 5:05 PM
You find it?
a

Anuj Dubey

05/14/2022, 7:03 PM
Try something like the following. set ::env(SYNTH_DEFINES) "MPRJ_IO_PADS=38" I’ve seen it somewhere but haven't tested it. Let me know if it works.
👍 2
a

aryap

05/14/2022, 8:37 PM
SYNTH_DEFINES
does the trick. thanks
👍 1
2 Views