is there an easy way to pass Verilog `define`s through the openlane flow to yosys for synthesis?

Yes cant remember exactly but search synth in the openlane options

thanks matt

You find it?

Try something like the following. set ::env(SYNTH_DEFINES) "MPRJ_IO_PADS=38" I’ve seen it somewhere but haven't tested it. Let me know if it works.

SYNTH_DEFINES

does the trick. thanks