open-source-silicon.dev

i also need a facility for overriding top-level verilog module parameters when invoking the flow. i’ve added this to `scripts/synth_top.tcl` ; i didn’t see an existing solution. is there a better way?
```if { [info exists ::env(SYNTH_PARAMETERS) ] } {
        foreach define $::env(SYNTH_PARAMETERS) {
                set param_and_value [split $define "="]
                lassign $param_and_value param value
                chparam -set $param $value $vtop
        }
}```

though i should probably have added it to `synth.tcl`

I don't see one in OL either.  In ORFS we just use a dict:
if {[info exist ::env(VERILOG_TOP_PARAMS)]} {
  dict for {key value} $::env(VERILOG_TOP_PARAMS) {
    chparam -set $key $value $::env(DESIGN_NAME)
  }
}