On a related note, has anyone ever tried making a ring oscillator in Verilog or VHDL? I tried some years ago and it made the tooling surprisingly unhappy. I was then advised that such a design could actually damage an FPGA.

There should be no way to "damage an FPGA" by implementing a ring oscillator or any other unclocked feedback circuit. It may fail to work, but it won't do any harm. On the other hand, FPGA software tools tend to guard against such a thing. Making a ring oscillator in verilog for an ASIC design is trivial; however, I don't think it can be done with RTL statements. You have to create a verilog netlist by directly instantiating the components you want. I have a tunable ring oscillator design for the striVe chip, written in verilog. The two things to look out for: (1) simulation of the verilog will fail. Such a structure can only be simulated in SPICE. To simulate anything, you will want to be able to replace the entire ring oscillator module with a simple (un-synthesizable) behavioral model that just generates a timed clock; and (2) static timing analysis tools will probably also fail. You will also want to be able to rip out the ring oscillator in order to be able to run static timing analysis on the rest of the design, namely by implementing the ring oscillator as a separate module and having a verilog wrapper module around the ring oscillator and the rest of the design. Bottom line is: Making a ring oscillator in verilog (for an ASIC) is a bit tricky but doable.

@Tim Edwards thanks for the detailed info !!!