@nvijayamanohar: This was an error in the scripts used to prepare the verilog files from source. iverilog does not understand the "specify" sections in the files. Unfortunately, we discovered that some of the "specify" section includes buffers that split a net and generate a delayed signal. The scripts did not catch those, and so did not modify the net names to prevent disconnected signals. The "proper" solution is to leave in the specify sections, and to have iverilog do at least the minimum necessary parsing to connect the nets, even if it does not know how to handle the delays (I don't know if anyone has tested whether iverilog already does this or not. It was generating fatal errors on some of the "specify" section syntax, so we elected to remove the whole section). The trivial workaround for the whole problem is to define FUNCTIONAL in the testbench verilog (or in the call to iverilog; e.g., "iverilog -DFUNCTIONAL") to force it to use the functional, and not the behavioral, models.