I am using sky130 libraries and facing the following issue. I wrote the RTL for a simple DFF and synthesized it and ran the GLS on the netlist. The verilog model of the flop in sky130 lib seems to be wrong and i am seeing q pin to be floating in the GLS output. This is because the verilog model is using some signals *_DELAYED (like D_DELAYED , RESET_B_DELAYED, etc) in it which are not driven inside the model. Have posted the snippet of the model along with this post. Please share me if you are aware of any known workarounds / limitations . Thanks in advance for help._

Interesting... Has anyone observed this before? @Tim Edwards @Tim 'mithro' Ansell

I ran into this issue a while back and the only fix I could find was to switch to a different simulation mode or to try to patch the cells manually

ok, thanks Anish

@nvijayamanohar: This was an error in the scripts used to prepare the verilog files from source. iverilog does not understand the "specify" sections in the files. Unfortunately, we discovered that some of the "specify" section includes buffers that split a net and generate a delayed signal. The scripts did not catch those, and so did not modify the net names to prevent disconnected signals. The "proper" solution is to leave in the specify sections, and to have iverilog do at least the minimum necessary parsing to connect the nets, even if it does not know how to handle the delays (I don't know if anyone has tested whether iverilog already does this or not. It was generating fatal errors on some of the "specify" section syntax, so we elected to remove the whole section). The trivial workaround for the whole problem is to define FUNCTIONAL in the testbench verilog (or in the call to iverilog; e.g., "iverilog -DFUNCTIONAL") to force it to use the functional, and not the behavioral, models.

Hi Tim ,

you may need to define UNIT_DELAY (iirc as

#1

)

Hi Tim / Anish , Also , want one more help . Have you tried to use yosys . I am facing issues with yosys for inferring latches. ie if i have latches in my RTL (proper latches not inferred latches ) , the synthesis is identifying them as latches but it is not inserting a lib cell for latch. DO you have any clue / workaround for this ?

this may be relevant - https://github.com/efabless/openlane/issues/40

Thanks a lot Anish

Is openlane the right place for @nvijayamanohar to file this? Is it already fixed? Should it go in the PDK or standard cell repo? I ask because as the slack channel limits to the last 10000 messages, these kinds of discussions are invaluable in future IMO

@Russell Friesenhahn: There are tools that can skim the contents of a slack workspace so that an archive web page can be made from it. We definitely need to do something like that. We already have important information in messages that have disappeared off the top of the discussions.

Thanks everyone for valuable feedback and quick help