Hello all, I have a question about the device details in the PDK docs. The stated performance of a of fanout 1 inverter, using low-vt nmos and regular pmos, does not match what I see in spice simulation. I'm looking at the docs here which say the minimum/maximum speed is 22/39 ps, but in simulation I measure 15/21 ps. Is there a reason for this difference? What does the manual mean when it says these are "EDR (e-test) specs"?

There may be a number of refinements needed to get spice to match what the library designers used. It could start from properly setting perimeter and area of source and drain of the devices in spice. Checking what a fanout of 1 means. What are thresholds this is measured against? Are source/drain contact resistances modeled in the device? Are all junction capacitances modeled? Are the metals and vias in the logic cell layout already considered? I would start by looking into this information.