Does anyone understand why the local interconnect in the SKY130 process is useful for SRAM / memories?
08/13/2021, 9:40 PM
My 10 cents here. In a memory array you need 2 metal layers for rows and columns, plus you need a higher level metal for supply rails. If the 6 transistor per cell structure (data latch + 2 access transistors) can be drawn using only local interconnect, you get a layout with no metal obstructions, so bitlines / row lines can run straight over the memory cell.
The Local interconnect (LIL) layer has a high resistivity, but for connecting memory cell transistors this is usually not a problem, since the transistors are small (low current) and interconnections are extremely short (memory cells are super compact).
08/13/2021, 10:10 PM
This is basically right. You can use m1 and M2 for word and bitlines without obstruction.