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#general
Title
# general
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Mitch Bailey

12/07/2021, 9:12 AM
Is there any interest in design reviews? I've seen some chips that pass LVS/DRC, but probably won't work as expected (power metal width, number of contacts,
li
as wires, etc.). How about setting up a channel where designers could post links to the layout/circuit and have others comment?
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Matt Liberty

12/07/2021, 10:24 PM
Is there any restriction on who can create a channel? I don't think so ...
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Maximo Balestrini

12/16/2021, 2:42 PM
Now that you mention
li
as wires, I've seen openlane use them in my project. Is that something completely wrong? Or is there something I could check to know that it wont be causing me problems?
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Matt Liberty

12/16/2021, 7:44 PM
@User it looks like droute.tcl needs "-bottom_routing_layer met1" to avoid li routing
I created #design-review since there a bunch of positive responses
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donn

12/16/2021, 8:35 PM
@User I'll get right on it.
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Mitch Bailey

12/16/2021, 10:42 PM
Thanks, @User. It'll be interesting to see what kind of response we get. Also what I can learn from other's reviews.
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Maximo Balestrini

12/17/2021, 12:25 AM
@User @User wanted to know a little bit more about the issues with using
li
for routing nets. If my design passes the openSTA checks, what problems could I have that the openlane flow doesn't alert me?
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Mitch Bailey

12/17/2021, 12:38 AM
I'm not sure how the routing resistance is translated into delays for the openSTA checks, but the pdk shows that li resistivity (12800mΩ/sq) is 100x greater than met1 (125mΩ/sq). https://skywater-pdk.readthedocs.io/en/main/rules/rcx.html#resistance-rules
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Matt Liberty

12/17/2021, 12:56 AM
it depends on where you are in the flow, either estimated parasitics or extracted but either way you should see the impact. It is intended for 'local interconnect' as the name suggests
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Maximo Balestrini

12/17/2021, 11:48 AM
Taking a quick look at the SPEF file I see that the resistances of those li1 nets are really big compared to the other layers. So I guess openSTA is taking that into account. I understand is not efficient to use them as routing wires, but what I wanted to know is if I should be worried that my submitted mpw-3 design uses them, even though it passed the STA with extracted parasitics
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Austin Rovinski

12/21/2021, 2:08 AM
Something to note is that the detailed router is not timing-aware. OpenSTA may say that it passes timing checks, but it doesn't mean it passed with a good solution. Avoiding high RC layers helps with both timing and power.
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