Someone knows how to setup and use the wishbone interface?

I have successfully written a number of wishbone interfaces now, all by just using the ones that Mohamed Shalan wrote for the caravel processor. The main thing is to use

cyc

and

stb

correctlly. The slave module can take as long as it wants to perform a read or write operation, and stalls the processor until it raises

ack

. A fairly simple example is the 1-pin GPIO interface in the Caravel SoC; see

caravel/verilog/rtl/gpio_wb.v

. This module implements a very simple memory-mapped register with read and write.

@User made a short video and demo of the caravel wishbone interface: