Ruediger Ehlers

12/28/2021, 12:09 PM
Regarding an Open Shuttle Caravel User project: When placing Macros and other components into the user project wrapper, I'm getting "[WARNING]: All internal macros will not be connected to power." as a warning. Do I need to be concerned? Sounds like a big problem to me, but then again it's only a warning. how can I make sure that all components on the user project will be powered?

Brandon Ong

12/29/2021, 3:04 PM
I'm also curious about this

Mitch Bailey

12/29/2021, 4:27 PM
@User Are you explicitly setting
? See

Wajeh ul hasan

12/29/2021, 6:52 PM
@User One easy way is to open the
and look at the power connections visually.

Sajjad Ahmed

12/30/2021, 6:06 AM
Yes I got the same warning but power connections were proper in generated GDS. But why it throws such warning then🤔

Ruediger Ehlers

12/30/2021, 10:08 AM
@User Thanks for your reply. No, I'm not explicitly setting them. But I'm only using the Sky130 SRAM macros so far, and according to that thread, if the power line names are "vccd1" and "vssd1", setting that varaible should not be necessary.

Mitch Bailey

12/30/2021, 11:33 AM
Do you have a powered gate level verilog top netlist? Does it look like the power connections are correct there?

Ruediger Ehlers

01/01/2022, 11:24 PM
@User Sorry for the late reply. I resurrected the project in which the warning occurred. The verilog top netlist is powered and the power connections are very straight forward (basically taken from the user project example). After setting the
explicitely, the warning did indeed vanish despite not deviating from the "vccd1" and "vssd1" names. Thanks for your help!
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