Regarding an Open Shuttle Caravel User project: Wh...
# general
r
Regarding an Open Shuttle Caravel User project: When placing Macros and other components into the user project wrapper, I'm getting "[WARNING]: All internal macros will not be connected to power." as a warning. Do I need to be concerned? Sounds like a big problem to me, but then again it's only a warning. how can I make sure that all components on the user project will be powered?
b
I'm also curious about this
m
@User Are you explicitly setting
FP_PDN_MACRO_HOOKS
? See https://skywater-pdk.slack.com/archives/C016H8WJMBR/p1640783370019900
w
@User One easy way is to open the
pdn.def
in
klayout
and look at the power connections visually.
s
Yes I got the same warning but power connections were proper in generated GDS. But why it throws such warning then🤔
r
@User Thanks for your reply. No, I'm not explicitly setting them. But I'm only using the Sky130 SRAM macros so far, and according to that thread, if the power line names are "vccd1" and "vssd1", setting that varaible should not be necessary.
m
Do you have a powered gate level verilog top netlist? Does it look like the power connections are correct there?
r
@User Sorry for the late reply. I resurrected the project in which the warning occurred. The verilog top netlist is powered and the power connections are very straight forward (basically taken from the user project example). After setting the
FP_PDN_MACRO_HOOKS
explicitely, the warning did indeed vanish despite not deviating from the "vccd1" and "vssd1" names. Thanks for your help!
👍 1