There are a few designs that have multiple macros that are a

Question

There are a few designs that have multiple macros that are activated independently < U0175T39732> < U0172QZ342D> If one of the macros has a power short logical or physical it may render the whole chip unusable In low power designs there are several ways to isolate macros and cut the power to the macros not in use Has anyone worked on low power designs with sky130 Would that be an idea for a course < U0174MP1W6Q> FWIW CVC not the verilog cvc can do power domain crossing verification including SCRC sub threshold current reduction circuit

Matthew Guthaus · Answer

I think that power domains are definitely one of the needed things in the flow Also better support for multiple clock domains

Kunal · Answer

We have done one workshop on low power using sky130 and Synopsys VCS Labs Course Is this something similar you were looking for < U0202PW2DFX> was TA for this course

Matthew Guthaus · Answer

I mean open source

Mitch Bailey · Answer

< U0174MP1W6Q> Looks about right

Matt Venn · Answer

I would like to add this feature to my multi project tools

Mitch Bailey · Answer

We need someone to develop a mosfet power switch and then figure out how to incorporate that into the macros Another mini power ring

Matt Liberty · Answer

< U0175T39732> would you be more specific about better support for multiple clock domains

Matthew Guthaus · Answer

< U018LA3KZCJ> This is referring to OpenLane not openroad It might be just my lack of knowledge but it was very difficult to specify a gated or muxed clock in OpenLane The clock port must be a module port specifically not an internal net for example so you need to add extra hierarchy to get it to work

Matthew Guthaus · Answer

And then there s only one clock frequency

Matthew Guthaus · Answer

I think you can only specify one port as well

Matt Liberty · Answer

In ORFS we have run designs with multiple clocks and gated clocks Multiple clocks are handled through SDC and clock gating is handled by yosys and CTS How do you specify the clock port in OL I m curious what it is connected to

Matthew Guthaus · Answer

Yes I m aware of how to do it with SDC This is the OpenLane basic config <https openlane docs readthedocs io en rtd develop configuration README html> You define three variables CLOCK PERIOD CLOCK NET and CLOCK PORT CLOCK NET can be a list and that is what CTS is called on CLOCK PORT must be a single port AFAIK

Matthew Guthaus · Answer

From the openlane scripts ```f info exists env CLOCK PORT amp amp $ env CLOCK PORT = create clock get ports $ env CLOCK PORT name $ env CLOCK PORT period $ env CLOCK PERIOD else create clock name VIRTUAL CLK period $ env CLOCK PERIOD set env CLOCK PORT VIRTUAL CLK ```

Matthew Guthaus · Answer

And all input output delays are fixed to that clock I suppose the answer is we should just be making our own SDC rather than relying on openlane

Matt Liberty · Answer

that s the ORFS answer

Matt Liberty · Answer

CTS will pick up clocks from STA automatically

Matthew Guthaus · Answer

I m not sure that is true in openlane

Matthew Guthaus · Answer

at least it wasn t in earlier releases

Matthew Guthaus · Answer

```puts INFO Performing clock tree synthesis puts INFO Looking for the following net s $ env CLOCK NET puts INFO Running Clock Tree Synthesis clock tree synthesis buf list $ env CTS CLK BUFFER LIST root buf $ env CTS ROOT BUFFER clk nets $ env CLOCK NET sink clustering enable sink clustering size $ env CTS SINK CLUSTERING SIZE sink clustering max diameter $ env CTS SINK CLUSTERING MAX DIAMETER set propagated clock all clocks ```

Matthew Guthaus · Answer

It does look like it will default to the CLOCK PORT if CLOCK NET is not defined ``` if info exists env CLOCK NET set env CLOCK NET $ env CLOCK PORT ```

Matt Liberty · Answer

if they just remove clk nets from CTS it will do the right thing

Matt Liberty · Answer

Actually it was already removed you are looking at an older version

Matthew Guthaus · Answer

I was looking at the mpw3 version