There are a few designs that have multiple macros ...
# general
There are a few designs that have multiple macros that are activated independently (@User @User). If one of the macros has a power short (logical or physical), it may render the whole chip unusable. In low-power designs, there are several ways to isolate macros and cut the power to the macros not in use. Has anyone worked on low-power designs with sky130? Would that be an idea for a course (@User)? FWIW, CVC (not the verilog-cvc) can do power domain crossing verification including SCRC (sub threshold current reduction circuit).
I think that power domains are definitely one of the needed things in the flow. (Also, better support for multiple clock domains...)
We have done one workshop on low power using sky130 and Synopsys VCS Labs Course Is this something similar you were looking for ? @User was TA for this course
I mean, open source.
@User Looks about right.
I would like to add this feature to my multi project tools
We need someone to develop a mosfet power switch and then figure out how to incorporate that into the macros. Another mini-power ring?
@User would you be more specific about "better support for multiple clock domains"?
@User This is referring to OpenLane, not openroad. It might be just my lack of knowledge, but it was very difficult to specify a gated or muxed clock in OpenLane. The clock port must be a module port, specifically, not an internal net, for example, so you need to add extra hierarchy to get it to work.
And then there's only one clock frequency.
I think you can only specify one port as well?
In ORFS we have run designs with multiple clocks and gated clocks. Multiple clocks are handled through SDC and clock gating is handled by yosys and CTS. How do you specify "the clock port" in OL? I'm curious what it is connected to...
Yes, I'm aware of how to do it with SDC. This is the OpenLane basic config: You define three variables CLOCK-PERIOD, CLOCK-NET, and CLOCK-PORT. CLOCK-NET can be a list and that is what CTS is called on. CLOCK-PORT must be a single port AFAIK.
From the openlane scripts:
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f {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
    create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
} else {
    create_clock -name __VIRTUAL_CLK__ -period $::env(CLOCK_PERIOD)
    set ::env(CLOCK_PORT) __VIRTUAL_CLK__
And all input/output delays are fixed to that clock. I suppose the answer is we should just be making our own SDC rather than relying on openlane.
that's the ORFS answer
CTS will pick up clocks from STA automatically
I'm not sure that is true in openlane...
at least it wasn't in earlier releases
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puts "\[INFO]: Performing clock tree synthesis..."
puts "\[INFO]: Looking for the following net(s): $::env(CLOCK_NET)"
puts "\[INFO]: Running Clock Tree Synthesis..."

    -buf_list $::env(CTS_CLK_BUFFER_LIST)\
    -root_buf $::env(CTS_ROOT_BUFFER)\
    -clk_nets $::env(CLOCK_NET)\
    -sink_clustering_size $::env(CTS_SINK_CLUSTERING_SIZE)\
    -sink_clustering_max_diameter $::env(CTS_SINK_CLUSTERING_MAX_DIAMETER)

set_propagated_clock [all_clocks]
It does look like it will default to the CLOCK-PORT if CLOCK-NET is not defined:
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if { ! [info exists ::env(CLOCK_NET)] } {
                        set ::env(CLOCK_NET) $::env(CLOCK_PORT)
if they just remove -clk_nets from CTS it will do the right thing
👍 1
Actually it was already removed - you are looking at an older version
I was looking at the mpw3 version.