I already designed the GPIO itself, just need to figure out the ESD part. Is ESD NFETs being connected in diode mode to VDDIO/VSSIO enough?

ESD events are short high voltage/high currents events. One of the most important design aspects is symmetry in you layout so that current is spread evenly over the structure and there is no current crowding. The latter could cause a hot spot during an ESD event. Due to high voltage also typically layouts may not be done with minimal design rules for the IO cells. IO transistor are often designed to have so called snapback behaviour to withstand ESD events. (see ESD protection). I did my own IO cell design in my IOTestVehicle project. As no design rules for ESD layout is provided for Sky130, I based the layout of my IO drivers on the

sky130_fd_io__(n|p)fet__con_diff_wo_abt_270v2

cells in the caravel/caravan gds file. On vdd and iovdd often an active clamp is used as one does not want to put resistors on a supply in the current path. Unfortunately I could not finish a design for that for this tape-out.