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#riscv
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# riscv
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Adam RIchardson

03/02/2022, 11:40 AM
Hi again all, is there any documentation for the CPU memory layout and implementation for the Caravel SoC? The linker script has changed quite a lot and it's no longer clear to me where sections should be placed. Has anyone seen a diagram?
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Zeeshan Rafique

03/06/2022, 5:50 AM
Hi, You might want to read these books: Chapter 4 for implementation: https://www.amazon.com/Computer-Organization-Design-RISC-V-Architecture/dp/0128122757
Chapter 2 or 3: which named “Assembly” for linkers and memory hierarchy: https://www.amazon.com/RISC-V-Reader-Open-Architecture-Atlas/dp/0999249118
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Adam RIchardson

03/07/2022, 9:35 AM
Thanks @User, I was more referring to the specifics for the Caravel SoC rather than a general overview of assembly and linkers
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Zeeshan Rafique

03/07/2022, 3:20 PM
Ah no worries, at least you should mention that in your message.
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