Hi again all, is there any documentation for the CPU memory layout and implementation for the Caravel SoC? The linker script has changed quite a lot and it's no longer clear to me where sections should be placed. Has anyone seen a diagram?

Hi, You might want to read these books: Chapter 4 for implementation: https://www.amazon.com/Computer-Organization-Design-RISC-V-Architecture/dp/0128122757

Thanks @User, I was more referring to the specifics for the Caravel SoC rather than a general overview of assembly and linkers

Ah no worries, at least you should mention that in your message.