James Kirkley

11/24/2020, 2:45 AM
I'm having problems delineating some of the layers on the OSU standard cells. I think I have a handle on Poly, Li, Met1 and Metal2 thru Metal5...which are not unlike PCB traces on a multi-layer board.. I think I have a handle Via1-Via4...which carry signals between layers, like PCB vias.. I think I have a handle on the N-WELL Diffusion layer which specifically sits under PMOS cells. MET1TXT and MET1PIN seem to hold strictly text labels. I assume that text is meaningless when it comes to the actual fabrication process. I'm still trying to wrap my brain around the rest. I believe LICON and MCON are via-like connectors, but don't know which layers they connect. The rest of these may be diffusions: TAP,DIFF,NSDM,PSDM,LVTN,NPC,STDCELL I'm guessing that the NDSM and PSDM are the NMOS and PMOS diffusions that sit directly under their respective gates. I'm also guessing that STDCELL is really the P-Substrate that initially covers the entire surface of the raw silicon disk before fabrication. Let me know if these guesses are right. That would leave TAP,DIFF,LVTN, and NPC Any help would be much appreciated.


11/24/2020, 3:11 AM
Have you had a chance to look at this diagram?


11/24/2020, 3:55 AM
STDCELL is a marker layer used by the DRC