cool, I was not able to reconcile the comments with the checks on the code, tried a few things but algorithm still got lost, probably better for him to take a look at his convenience, I posted the DEF but no support files, I assumed sw130 is available and hope it will reproduce, also tried make global_route_issue, but failed miserably on my env.

Is the source verilog shareable? I can load in the DEF for routing but I might need a gate netlist

is just a minimalistic riscv 32 from a colleague, may become public domain soon, I could ask him about uploading the gate netlist, the reason I didn’t upload was because my global route script didn’t show a dependency:

if {![info exists standalone] || $standalone} {
  # Read lef
  read_lef $::env(TECH_LEF)
  read_lef $::env(SC_LEF)
  if {[info exist ::env(ADDITIONAL_LEFS)]} {
    foreach lef $::env(ADDITIONAL_LEFS) {
      read_lef $lef
    }
  }

  # Read liberty files
  foreach libFile $::env(LIB_FILES) {
    read_liberty $libFile
  }

  # Read design files
  read_def $::env(RESULTS_DIR)/4_cts.def
}

if {[info exist ::env(FASTROUTE_TCL)]} {
  source $::env(FASTROUTE_TCL)
} else {
  fastroute -output_file $::env(RESULTS_DIR)/route.guide \
            -max_routing_layer $::env(MAX_ROUTING_LAYER) \
            -unidirectional_routing true \
            -layers_adjustments {{2 0.5} {3 0.5} {4 0.5}  } \
            -overflow_iterations 100 \
            -verbose 10

Let me know if you think is still needed, I can check with him and upload 4_cts.v

Ok, I will try it. But I don't think the app is exited that's is why the verilog is not read back in

What do you mean? should both be read in for this step? I was reading through slack messages I was thinking this may be related to pin/grid alignment (there is a comment from @Tim Edwards), haven’t had a chance to check, nor have an easy method.