large designs can trigger that

log tail?

Either way I think we'll need a testcase to debug if possible.

Same error when PL_ROUTABILITY_DRIVEN is set to false

Oh the default is false anyways

Can you provide a test case for this and open an issue?

Completely unrelated

The opendp failure is related to escaping some signal names. My clock is io_in[17]. I need to escape the [] in config.tcl but not in base.sdc or else STA won't recognize the clock. However, or_opendp.tcl complains if I don't have it escaped:

invalid command name "17"
    while executing
"17"
    ("uplevel" body line 1)
    invoked from within
"uplevel #0 ${cmd}"
    (procedure "set_log" line 3)
    invoked from within
"set_log ::env($index) $escaped_env_var $::env(GLB_CFG_FILE) 1"
    (procedure "save_state" line 9)
    invoked from within
"save_state"
    (procedure "flow_fail" line 6)
    invoked from within
"flow_fail"
    (procedure "try_catch" line 25)
    invoked from within
"try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/or_opendp.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(opendp_log_file_tag)..."

This actually could be what changed for global routing too...

opendp rather

I don't see a read_sdc in or_opendp.tcl

The log output is useless.

It's reporting overlaps then segfaults [WARNING DPL-0005] Overlap check failed (16972).

repeater448 overlaps ANTENNA_repeater448_A repeater449 overlaps ANTENNA_repeater449_A repeater451 overlaps ANTENNA_repeater451_A [ERROR]: during executing: "openroad -exit /openlane/scripts/openroad/or_opendp.tcl |& tee >&@stdout /project/openlane/user_project_wrapper/runs/user_project_wrapper/logs/placement/29-opendp.log" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: child process exited abnormally [ERROR]: Please check openroad log file [ERROR]: Dumping to /project/openlane/user_project_wrapper/runs/user_project_wrapper/error.log

you mentioned having macros - are there placement sites in the channels ?

I have seen a case recently where the channel was so narrow no instances could be placed there

One dumb question. There is now a config.json in addition to config.tcl with duplicate information. Why are they both there?

I am not much of an openlane expert, I mostly work on openroad. @User can you explain config.json vs config.tcl?

Do note that I mean only Tcl will be loaded. JSON will be ignored entirely. If the tcl config's missing, it will attempt to load a json config. If the json config's missing as well, flow.tcl will throw an error.

After wrestling with a fresh install of openlane/pdk, I can reproduce this with or_opendp again:

invalid command name "17"
    while executing
"17"
    ("uplevel" body line 1)
    invoked from within
"uplevel #0 ${cmd}"
    (procedure "set_log" line 3)
    invoked from within
"set_log ::env($index) $escaped_env_var $::env(GLB_CFG_FILE) 1"
    (procedure "save_state" line 9)
    invoked from within
"save_state"
    (procedure "flow_fail" line 6)
    invoked from within
"flow_fail"
    (procedure "try_catch" line 25)
    invoked from within
"try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/or_opendp.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(opendp_log_file_tag)..."
    (procedure "detailed_placement_or" line 6)
    invoked from within
"detailed_placement_or"
    (procedure "run_routing" line 32)
    invoked from within
"run_routing"
    (procedure "run_routing_step" line 10)
    invoked from within
"[lindex $step_exe 0] [lindex $step_exe 1] "
    (procedure "run_non_interactive_mode" line 43)
    invoked from within
"run_non_interactive_mode {*}$argv"
    invoked from within
"if { [info exists flags_map(-interactive)] || [info exists flags_map(-it)] } {
        puts_info "Running interactively"
        if { [info exists arg_values(-file)..."
    (file "/openlane/flow.tcl" line 356)
make[1]: *** [Makefile:43: user_project_wrapper] Error 1
make[1]: Leaving directory '/home/mrg/openram_testchip/openlane'
make: *** [Makefile:70: user_project_wrapper] Error 2

The "17" is in the name of my clock in my base.sdc or my config.tcl file:

set ::env(CLOCK_PORT) {io_in[17]}

If I don't use the base.sdc, it still does the above so it must be something with the config.tcl. I have the name escaped there:

set ::env(CLOCK_PORT) {io_in\[17\]}

If I look at the generated SDC files, however, the name is unescaped:

mrg@diode ~/openram_testchip/openlane/user_project_wrapper/runs/user_project_wrapper (main)$ find . -name \*.sdc -exec grep create_clock {} \; -print
create_clock -name io_in[17] -period 30.0000 [get_ports {io_in[17]}]
./results/cts/user_project_wrapper.cts.sdc
create_clock -name io_in[17] -period 30.0000 [get_ports {io_in[17]}]
./tmp/floorplan/4-verilog2def.sdc
create_clock -name io_in[17] -period 30.0000 [get_ports {io_in[17]}]
./tmp/placement/23-resizer_timing.sdc
create_clock -name io_in[17] -period 30.0000 [get_ports {io_in[17]}]
./tmp/placement/21-resizer_timing.sdc
create_clock -name io_in[17] -period 30.0000 [get_ports {io_in[17]}]
./tmp/placement/16-resizer.sdc

So there are two questions: 1. why isn't write_sdc escaping the name properly? 2. why is or_opendp using the SDC at all?

@User ^^

OH, so this failure is actually during routing when it is trying to legalize the diodes. This is why timing is enabled...

GAH, and it can't legalize the diodes because they are "sprayed" all over the macros and can't be moved outside of the macros.

But spray won't work if you have macros now

"Spray diodes"

Specifies the insertion strategy of diodes to be used in the flow. 0 = No diode insertion, 1 = Spray diodes, 2 = insert fake diodes and replace them with real diodes if needed. 3= use FastRoute Antenna Avoidance flow, 4 = Use Sylvian's Custom Script for diode insertion on design pins and smartly inserting needed diodes inside the design, 5 = a mix of strategy 2 and 4. (Default: 3)

Yes, I had an older version during MPW2 🙂

Looks like those are in conflict with eachother. Maybe spray puts them randomly and then tries to connect them to each pin?

I think 3 used to not work because they were using a different router before, if I recall?

TritonRoute vs FastRoute?

from what I can see in routing.tcl it looks to like 1 is closer to "A diode is inserted for each PIN and connected to it. " versus spraying but I guess that doesn't match your experience

it looks like it is trying to put a diode on each pin directly and then let detailed placement legalize it

that's potentially a lot of diodes so it might not be possible to legalize them in a dense enough design area

however I would expect that would lead to diodes on the pins not deep inside the macros

This is all after routing

the design will be 100% full after filler insertion and nothing else will fit

There are calls to ins_fill_cells after ins_diode_cells but before detailed_place_or

So it may take up the space and not be able to legalize

Yeah, it runs ins_fill_cells before legalization of the diodes. That is the problem.

@User ^^