Is there is any way to avoid changing manually inserted cell

Question

Is there is any way to avoid changing manually inserted cells during resizer phase openroad or resizer tcl repair design slew margin $ env PL RESIZER MAX SLEW MARGIN cap margin $ env PL RESIZER MAX CAP MARGIN Background I see tool is modifying manually inserted DELAY cells to buffer Is there is any option to set dont touch cells to exclude manually inserted cells

Vijayan Krishnan · Answer

set dont use $ env DONT USE CELLS < U018ZHJ2A48> Do we have set dont touch for cells during runtime

Dinesh A · Answer

DONT USE CELLS are list cells should not be used in design

Vijayan Krishnan · Answer

set dont touch get ports whether this option available for cells need to explore

Vijayan Krishnan · Answer

manually inserted cells Can you explain briefly

Dinesh A · Answer

Typically we manually insert Standard cell for clock Mux and Internal clock source with Buffer and Interface Timing with Hold fix cells Typically other commerical tools have option to say don t touch attribute to a instance These instance are not touch by the tool optimization function

Dinesh A · Answer

Currently during Yosys synthesis phase i see these cells are retained by resizer logic blindly changing the cells to higher drive buffers

Vijayan Krishnan · Answer

do you have dont touch variable in your lib for those manually inserted cells

Dinesh A · Answer

This will not a lib attributes amp These are not special cells This is constraint to tool to avoid modifying specific instances

Dinesh A · Answer

My analysis says the changes is happening in src rsz src Resizer cc Resizer resizeToTargetSlew const Pin drvr pin bool update count Instance inst = network gt instance drvr pin LibertyCell cell = network gt libertyCell inst if cell bool revisiting inst = false if hasMultipleOutputs inst revisiting inst = resized multi output insts hasKey inst debugPrint logger RSZ resize 2 multiple outputs revisiting inst revisit resized multi output insts insert inst ensureWireParasitic drvr pin Includes net parasitic capacitance float load cap = graph delay calc gt loadCap drvr pin tgt slew dcalc ap if load cap gt 0 0 LibertyCell target cell = findTargetCell cell load cap revisiting inst if target cell = cell debugPrint logger RSZ resize 2 gt sdc network gt pathName drvr pin cell gt name target cell gt name if replaceCell inst target cell true amp amp revisiting inst amp amp update count resize count ++ return false Currently i am locally hacking this logic

Dinesh A · Answer

I see this logic blindly changes any cells load cap gt 0 0 with higher drive equivalent cells

Vijayan Krishnan · Answer

ok wait for update from < U018ZHJ2A48>

Austin Rovinski · Answer

Sorry I don t check this slack often Technically ODB supports this setting with `setDoNotTouch ` and checking with `isDoNotTouch ` but I don t think any code uses this functionality Something you can try is saving the DEF modifying the inst as `FIXED` and then reloading it If that doesn t work you can open a bug report feature request to support `doNotTouch` in resizer

Austin Rovinski · Answer

A temporary hack is that I know resizer ignores special nets So if you mark that net as special then it will ignore the net as well as any instances attached to it But this may yield undesirable results