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Anton Blanchard
02/17/2022, 3:51 AM@User @User Starting a thread to discuss the CTS results I'm seeing on my design
Firstly, CTS on my macros looks reasonable. Here's the register file. Skew is good, and overall delay seems reasonable (maybe a bit high?)
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report_clock_skew
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Clock CLK
Latency CRPR Skew
_59544_/CLK ^
3.90
_59544_/CLK ^
3.53 -0.37 0.00CTS on my top level design is not so good. Very high skew and very high max delay:
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report_clock_skew
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Clock wb_clk_i
Latency CRPR Skew
_129424_/CLK ^
12.04
_127204_/CLK ^
6.52 0.00 5.52/tmp/m
Matt Liberty
02/17/2022, 4:24 AMCan you highlight 129424 in the picture? You have some parts of the clock tree going way off near the top of the design.
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Anton Blanchard
02/17/2022, 4:25 AM@User will do
Interesting that the quickest and slowest clock path are very close to each other, just under the top macro and in the center horizontally
I'll look through the CTS logs to see if I can get more info on these two paths
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Matt Liberty
02/17/2022, 4:58 AMThat's surprising. Can you package the cts step as a testcase to look at? Its hard to see too much from the image
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Anton Blanchard
02/17/2022, 4:59 AMYeah, I'll do that
There's a false path between the main clock and the jtag clock. Fixing my timing constraints and retesting.
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mehdi
02/17/2022, 7:42 PM@User Thanks for sharing this. if you aren't skipping the in-to-reg paths or did not update your sdc to take into account multicorners. Then you ll end up with skews like this. Is the paths failing part of the "async_group"?
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Anton Blanchard
02/17/2022, 10:57 PMThe skews are much better now I've separated the main clock and jtag clock. This is what I have for my sdc file now (does it look reasonable?) https://github.com/antonblanchard/microwatt-mpw5/blob/20220218/openlane/user_project_wrapper/base.sdc
I'm completely out of my depth with multicorner timing, so let me know if you spot any issues.
I haven't constrained the rest of the I/Os since they are just used as GPIOs