Anton Blanchard

02/22/2022, 2:17 AM
I've started investigating some CTS issues - clock tree skew and clock delay are quite high
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Clock user_clock2
Latency      CRPR       Skew
_127845_/CLK ^
_122164_/CLK ^
   5.77     -0.13       2.31
That's using
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set ::env(ROOT_CLK_BUFFER) sky130_fd_sc_hd__clkbuf_16
set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_2 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8"
Seems a bit strange we'd need a
on the root, considering with are only driving 2 gates. Also strange, is we seem to be using a
for the leaf nodes, so I guess
is for both root and leaf
I also wonder if CTS is making intelligent decisions with the choice of buffers. As an experiment I just gave it clkbuf_4:
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set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_4}
set ::env(CTS_ROOT_BUFFER) {sky130_fd_sc_hd__clkbuf_4}
A slight improvement:
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Clock user_clock2
Latency      CRPR       Skew
_123645_/CLK ^
_127643_/CLK ^
   5.74     -0.13       2.03
Apart from that, I notice we are added a large number of buffers along wires. Seems like too many to me. I tried modifying that behaviour:
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unsigned maxWirelength = (_charBuf->getHeight() * 10)
                            * wirelengthIterations;  // Hard-coded limit
   if (_options->getWireSegmentUnit() == 0) {
-    unsigned charaunit = _charBuf->getHeight() * 10;
+    unsigned charaunit = _charBuf->getHeight() * 200;
   } else {
That helped quite significantly:
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Clock user_clock2
Latency      CRPR       Skew
_124062_/CLK ^
_130501_/CLK ^
   3.61     -0.24       1.63
I was thinking about the over buffering and realise the change above isn't what we want. Would it make sense instead to call
against all the buffer cells and pick the shortest length and set
to that?