In MPW-6, Any suggestion on how control the pdn_cfg.tcl to create 8 core ring (vccd1 vccd2 vdda1 vdda2 vssd1 vssd2 vssa1 vssa2) and power strip only for vccd1 vssd1 nets. My design needs only vccd1/vssd1 power and I don't have enough space to fit all 8 power strips between hard macro. In MPW-3/MPW4/MPW-5 I used to do some hack in PDN scripts to achieve this. But MPW-6 PDN scripts are once again changed..

Why do you want rings for supplies you aren't using?

We need to have ring with all the power supplies for MPW pre-check to passes.

Do you know why they require this?

MPW pre-check expects user project gate level netlist having all the power pins even though digital logic consumes one set of power supply. Also caravel + User project empty GDS cross-check will fails if core ring does not have all the 8 power rails. @User can share more details

There is no option currently to create useless rings. We could add one but then we would have to modify the flow the make the user specify which ones to include. @User can this requirement be relaxed?

@User Power supply are driven from top-level caravel block, which will not know the Power consumed by individual user project. It expect 8 power ring to feed power to user area. I see this need to handle in Openlane script/flow only?. Default 8 power strips requirement making me to keep minimum 8 power-strip space between each hard macros. One my project has multiple Macros and does not have enough free space to support this. In MPW-3/4/5 I have made some hack in both PDN source and flow to avoid unused power strips generation. Look like there are new changes in PDN source and flow changes in MPW-6 and my scripts are not working .. I am Looking for clean way to working with Openlane flow. @User or @User can comment if there is way to relax this requirement in MPW Pre-check sign-off.

@User: I don't know how the PDN scripts are written, but as far as I am concerned your design should be able to use any one to all four of the provided supplies. The power ring itself is fixed, and not part of the user area per se, because it has to match the connections being made to it from the chip top level. But it sounds like your issue is just to keep the power stripes in the interior limited to only vccd1 and vssd1, which ought to be doable. You will need to ask Mohamed Shalan's group. . . Try Marwan Abbas (if not him, then at least he can find you the right person to talk to). Otherwise you do have a couple of options: (1) Merge together vccd1 and vccd2 (assuming that's possible with the PDN scripts---again, it ought to be possible to do that, but doesn't necessarily mean that it is); (2) Use the caravan chip, in which case you can design the power ring any way you want, the only issues being that you will have to manually connect up the power supplies to the wrapper edge, and you will lose 11 GPIO pins. But I think it's better to just raise the issue and flag it as a major error if the PDN scripts cannot accommodate what you want to do.

I have raised Openlane enhancement request: https://github.com/The-OpenROAD-Project/OpenLane/issues/1096#issue-1238025370

@Marwan Abbas can you check into this please?