@Tim Edwards is there a schematic of the IO ring that you could please share for both Caravel and Caravan? Thanks

You mean schematic like something drawn in xschem? All verification has been done against a verilog netlist.

Basically I would like to understand the ESD arrangement a bit more. Specifically about the isolation and ESD between the 8 power pads. Are the 4 ground pads connected together via antiparallel diodes for instance? Thanks

The verilog netlist is in the caravel repo.

verilog/gl/chip_io.v

or for analog,

verilog/gl/chip_io_alt.v

. The associated lower level spice is in

$PDK_ROOT/sky130?/libs.ref/sky130_fd_io/spice/sky130_fd_io.spice

and

$PDK_ROOT/sky130?/libs.ref/sky130_fd_io/spice/sky130_ef_io.spice

@Adil Malik: There is also a drawing of the power domains in the caravel repository under

docs/source/_static/voltage_clamp_arrangement.svg

. A schematic would be better, of course, but that diagram at least shows where the clamps and diodes are on the power domain, and where they are located around the padframe. In the diagram, "HV" refers to a high-voltage (3.3V domain) clamp, "LV" refers to a low-voltage (1.8V domain) clamp, and "BB" refers to back-to-back diodes coupling ground domains.

@Tim Edwards This is exactly what I needed thank you very much. One quick question about this stuff: is it OK to substitute anywhere I read 3.3V with 5V if I intend to run VDDIO and VDDA at 5V (and VCCD at 1.8V)?

Yes, that's correct.