Adil Malik
10/20/2022, 7:40 PMTim Edwards
10/20/2022, 8:28 PMAdil Malik
10/20/2022, 8:33 PMAdil Malik
10/20/2022, 8:50 PMMitch Bailey
10/20/2022, 10:14 PMverilog/gl/chip_io.v
or for analog, verilog/gl/chip_io_alt.v
. The associated lower level spice is in $PDK_ROOT/sky130?/libs.ref/sky130_fd_io/spice/sky130_fd_io.spice
and $PDK_ROOT/sky130?/libs.ref/sky130_fd_io/spice/sky130_ef_io.spice
Tim Edwards
10/21/2022, 3:08 PMdocs/source/_static/voltage_clamp_arrangement.svg
. A schematic would be better, of course, but that diagram at least shows where the clamps and diodes are on the power domain, and where they are located around the padframe. In the diagram, "HV" refers to a high-voltage (3.3V domain) clamp, "LV" refers to a low-voltage (1.8V domain) clamp, and "BB" refers to back-to-back diodes coupling ground domains.Adil Malik
10/21/2022, 11:08 PMTim Edwards
10/21/2022, 11:12 PM