Hello altruists, Can anybody help me with chip level integration? I hardened macro, but cannot integrate in the core module. I copied their design in to my openlane design folder, hardened them one by one, and fixed some errors while hardening. I am not sure if the fix are correct. I am trying to run the design defined in this repo: https://github.com/Baungarten-CINVESTAV/CustomFPGA Error: LVS reports: net count difference = 92 device count difference = 0 unmatched nets = 130 unmatched devices = 20 unmatched pins = 0 property failures = 0 Total errors = 242

@Mahfuzul Haque Happy to help. Most LVS discussions these days are at https://matrix.to/#/#lvs:fossi-chat.org Can you share your lvs report file that has more detailed errors? The screen log should show the file name.

@Mitch Bailey The log says: [STEP 28] [INFO]: Running LVS (log: designs/FPGA_top/runs/RUN_2025.10.30_01.22.41/logs/signoff/28-lvs.lef.log)... [ERROR]: There are LVS errors in the design: See 'designs/FPGA_top/runs/RUN_2025.10.30_01.22.41/reports/signoff/28-fpga_top.lvs.rpt' The 28-fpga_top.lvs.rpt file only contains the lines I provided earlier. If you have OpenLane, you may try hardening the macros form their repo.

@Mahfuzul Haque Can you share

designs/FPGA_top/runs/RUN_2025.10.30_01.22.41/logs/signoff/28-lvs.lef.log

?

Here you go. @Mitch Bailey

@Mahfuzul Haque Looks like the power grid is not connected in the layout. Can you open the layout and check the connectivity?

@Mitch Bailey Here is a layout of one of the macros. I can open them but don't know how to check the connectivity.

@Mahfuzul Haque I don’t think I’ll be able to tell anything from just one macro. Do you have the gds of the full design that’s failing LVS?

@Mitch Bailey The final GDSII. Please check and let me know.

I assume this is sky130?

@Mitch Bailey yes

Looking at the layout, I see that there are 2 types of macros. The

grid_*

macros have up to metal5 while the other macros have up to metal4. None of the macros appear to be connected to the power grid. I don’t see any lef files in the repo. Maybe they’re created when you run openlane for each macro. I think the macros should only have up to metal4. Then the top level routing will connect everything with metal5. Looking at the config.json files in the repo,

grid_clb

doesn’t specify a max routing layer. I’d check the

grid_*

configurations to be sure the max routing layer is metal4. Regenerate. Then check the layout to be sure that all macros have the metal5 power grid routed over the top. To figure out why

clb*

doesn’t connect, can you send one of the lef files?

@Mitch Bailey Thank you very much for your analysis. Could you please tell me which tool you are using to view the GDS files?

klayout.

Should all the macros be connected to the power grid through met4?

Right. The top metal layer of all the macros should be metal4.