@SUMANTO KAR @Tim Edwards so this is kind of a follow-up to my previous post on magic. I managed to clean up all inverter layout DRC errors and extracted the post-layout netlist (without parasitics). Now I run netgen and it seems all the device counts are right (see attachment <comp.out>), but the netlist pins do not match, see the following:

Subcircuit pins:
Circuit 1: inverter                        |Circuit 2: inverter                        
-------------------------------------------|-------------------------------------------
*in                                        |*out **Mismatch**                          
*out                                       |*in **Mismatch**                           
**no match**                               |vss                                        
**no match**                               |vdd                                        
---------------------------------------------------------------------------------------
Cell pin lists for inverter and inverter do not match.

And then I went back to the magic extracted SPICE netlist from the layout (attached as well) and the netlist is missing the power pins for the inverter (vss and vdd are gone somehow, see the

.subckt inverter in out

):

X1 a_n78_n150# a_n129_n238# a_n173_n150# a_n275_n324# sky130_fd_pr__nfet_01v8 ad=4.5e+11p pd=3.6e+06u as=4.425e+11p ps=3.59e+06u w=1.5e+06u l=180000u
X2 a_18_n150# a_n33_172# a_n78_n150# a_n275_n324# sky130_fd_pr__nfet_01v8 ad=0p pd=0u as=0p ps=0u w=1.5e+06u l=180000u
.ends

.subckt sky130_fd_pr__pfet_01v8_KG2LE3 a_n78_n100# a_n173_n100# a_n129_n197# a_18_n100#
+ a_63_n197# a_114_n100# w_n311_n319# a_n33_131#
X0 a_18_n100# a_n33_131# a_n78_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=3e+11p pd=2.6e+06u as=3e+11p ps=2.6e+06u w=1e+06u l=180000u
X1 a_114_n100# a_63_n197# a_18_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=2.95e+11p pd=2.59e+06u as=0p ps=0u w=1e+06u l=180000u
X2 a_n78_n100# a_n129_n197# a_n173_n100# w_n311_n319# sky130_fd_pr__pfet_01v8 ad=0p pd=0u as=2.95e+11p ps=2.59e+06u w=1e+06u l=180000u
.ends

.subckt inverter in out
XXM1 in VSUBS out out in in out out sky130_fd_pr__nfet_01v8_N39HBR
XXM2 out out in out in out w_762_728# in sky130_fd_pr__pfet_01v8_KG2LE3
.ends

The layout is attached for your reference, what could be the possible cause of this? Thanks!

It looks to me like the source/drain contacts are covering the entire source and drain, so that the output, ground, and power are all shorted together. That would correlate with the extracted netlist---there are only effectively two pins, one is "in" and the other is "out/vss/vdd" (it had to pick one, which happens to be "out").

@Chris please check if this works: https://open-source-silicon.slack.com/archives/C045AKFCBB9/p1665556240078439

Solved! Yes after I split the source/drain contact the problem was solved! It was not very clear until I used

cif see MCON

to make the contacts visible.

Great @Chris