@mehdi has left the channel

<!channel> VSD-HDP - Dream VLSI program for every VLSI aspirant [last 3-days] Look at the image and doesn't it look like a dream VLSI program, where RTL-GDS-Tapeout-Tape In-Chip mounting-Board design is something which every VLSI fresher and professional aspires to witness once in their career? VSD was 100% involved in doing all the above steps for more than 40+ in-house designs and it can't get more exciting than this It was my dream when I was a student and so we are happy that such a curriculum is a dream come true for everyone. The image shows the reason why different areas of electronics and system design exist in the first place and what it takes to cover all 6 steps shown in the image. The HDP program covers Steps 1) and 2) in detail. But it doesn't stop there. For participants who complete the program 100%, VSD will personally love to engage with them to complete 3), 4), 5) and 6) for zero additional cost VSD-HDP program black Friday sales end in 3-days and below is the registration link with more details https://www.vlsisystemdesign.com/hdp/ Thanks to efabless, Google, and Skywater for being the reason for using open-source EDA tools and enabling students to collaborate freely across organizations even after the course is over as there are no legal agreements to use open-source technology. With the advent of SKY130 PDKs, it enables easy access to tape-out shuttles which are currently sponsored by Google. So all the best and we will see all of you in the HDP program, where you get access to all Udemy courses for free

<!channel> VSD-HDP Black Friday Sales end tomorrow This is a gentle reminder that VSD-HDP black Friday sales end tomorrow. Refer to the below link for more details about various projects: https://www.vlsisystemdesign.com/hdp/

<!channel> FPGAs - Ascending and descending processes of knowledge I have a question: If a student or fresher wants to learn this exciting field of VLSI, digital design and FPGA, what do you think is the best process to acquire knowledge? Ascending process - In this one, we utilise our senses, mind, and intellect to explore digital design, discover VLSI, and conclude about the nature of FPGAs which proves to be useful to quickly test out a logic. It's a process of acquiring knowledge where one endeavours to enhance the frontiers of understanding through self-effort. It's a great way to self-learn, except it's laborious, imperfect and time-consuming. It might take you more than 8-9months to figure out the entire process from scratch. The ascending process is exceedingly time-consuming, and we may not even be able to complete the enquiry in our lifetime. We can also not be sure about the validity of our conclusions unless we do multiple experiments Descending process - It's a process of acquiring knowledge where someone who is a perfect authority on the knowledge passes it down to another who wishes to learn. Take an example of this FPGA workshop. We could either try to do it by the ascending process, where we speculate about its principles with our own intellect and then reach conclusions or we could do it by the descending process, where we approach a good teacher of the subject. The descending process gives us instant access to the deepest secrets of FPGAs. If our instructor has perfect knowledge of VLSI and FPGAs, then it is very straightforward - simply listen to the science from the instructor for 5-days during the workshop and digest what they say. This descending process of receiving knowledge is both easy and faultless So where's the problem these days? Merely imparting invaluable knowledge about FPGAs to someone is not enough. The recipients of that knowledge must appreciate its value and have faith in its authenticity. Only then will they put in the effort required to implement it practically in their lives. That's where VSD works with the passionate instructors in the field, takes enough time to build the labs and then delivers. Why do students trust VSD? Every year, thousands of self-help books and videos are released, which present the author's solutions to the problems encountered in life. These resources may be helpful in a limited way, but because they are based upon the ascending process of attaining knowledge, they might have flaws. On other hand, as thousands of participants must have witnessed by now, VSD workshops are delivered from a perfect source, and hence the knowledge you receive is infallible and trustworthy Want to witness how a VSD FPGA workshop looks? Register for a 5-day workshop using the link below: https://www.vlsisystemdesign.com/fpga/ Thanks to our anonymous corporate sponsors that helped us to bring down the cost of the workshop by 40%. All the best and happy learning

<!channel> VSD-IAT, OpenFPGA and SKY130 - Powerful Talent machine In this age where we need new kinds of talent in the VLSI industry, it's time to build a new kind of structured talent generation machine. Thanks to Google, SKY130 and OpenFPGA for making this happen. For anyone who has attended all VSD-IAT workshops in past years, you might be able to figure out one common node across all workshops - Opensource Skywater 130nm Now, why is that important? It is important for 2 reasons - "*open source*" and "*real*". Students, freshers and professionals start learning at a different level using real foundry PDKs which is good for multiple reasons, out of which the primary reason is the announcements of so many foundries globally, which in turn demands talent who has sufficient knowledge of at least one foundry node Every VSD-IAT (Intelligent Assessment Technology) workshop was built as separate projects as all labs had to be ported to the SKY130 technology node. Now a fresher who goes through the VSD-IAT workshop is by default aware of PDK terms and is also aware of real challenges one might face while using real foundry data. The various topics covered in workshops are an industry ASIC flow as shown in the image. It's globally tested and proven by 12,000+ students So how are FPGA and SKY130 related? FPGA is a parallel arm to ASIC, which is much faster for prototyping. And many videos are already available on websites on how to program FPGAs. The part which we wanted to do differently in this workshop was to show how to build an FPGA fabric using SKY130 and compare your FPGA fabric with proprietary FPGA tools. This exercise helps FPGA companies to get fresh FPGA talents with unique skills which are currently scarce. Register for the last workshop of this year (last 3 days). Here's the registration link for more details https://www.vlsisystemdesign.com/fpga/ Many new workshops and topics related to SKY130 will be added in upcoming years which goes below and above the flow shown in the image. So stay tuned to VSD in 2023

<!channel> Last day to register for last FPGA workshop This is a gentle reminder that you have one more day to register for the last workshop of the year - FPGA - Fabric, design and architecture Here's the registration link- https://www.vlsisystemdesign.com/fpga/ Here's the day-wise content: Day1: 1. Introduction to FPGA 2. Counter example using Vivado 3. Counter Verilog explanation and implementation using Vivado 4. Vivado timing, power, and area measurement for counter 5. Introduction to VIO Day2: 1. Introduction to OpenFPGA and VTR (verilog-to-routing) 2. Introduction to VPR (versatile-place-and-route) using basic Earch fabric 3. Counter example using VPR/VTR openfpga flow Day3: 1. Introduction to basic RISC-V core – rvmyth 2. Rvmyth – Vivado RTL to synthesis flow 3. Rvmyth – Vivado Synthesis to bitstream Day4: 1. Introduction to opensource SOFA FPGA fabric 2. Steps to run counter example on SOFA 3. Characterize counter example in terms of area and timing 4. Post-implementation netlist and simulation using SOFA Day5: 1. Steps to run RISC-V Core - on SOFA 2. Characterize RVmyth in terms of performance and area 3. Steps to generate rvmyth post-implementation netlist 4. Confirm RVmyth on SOFA behavioral simulation using Vivado All the best and happy learning

@E. Tamura has left the channel

channel vsdsquadron - Journey from training to product for "effective" semiconductor workforce development I am so happy to present vsdsquadron rev_0, which is an educational board especially for RISC-V and semiconductor learning and training. This is one of the many projects built as a part of VSD-IIIT Bangalore industry-academia collaboration. This would not have been possible without immense support from Google, Efabless, OpenROAD and (last but very powerful) Skywater technologies. Read below blog for more details https://www.linkedin.com/posts/kunal-ghosh-vlsisystemdesign-com-28084836_this-pic-represents-possible-achievements-activity-7018441911917051904-zMBF?utm_source=share&amp;utm_medium=member_desktop

<!channel> Take Your Physical Design Skills to the Next Level with open-source and Win a Spot in our Research Program Are you ready to take your physical design skills to the next level? Join the OpenLANE Physical Design workshop from 25th Jan, and you'll not only gain valuable knowledge and skills in the field, but you'll also have the chance to win a spot in our upcoming VSD research program for FREE The OpenLANE Physical Design workshop is designed for professionals and students who want to deepen their understanding of physical design and learn about the latest tools and techniques in the field. The workshop will be led by experienced industry experts who will share their knowledge and experience in the field. Participants will have the opportunity to work on hands-on exercises and projects to apply what they have learned. And those who complete the workshop will be eligible to participate in a VSD research program starting on February 4th. The research program will allow participants to work on cutting-edge projects and conduct original research under the guidance of industry experts. This is a unique opportunity to gain real-world experience and make valuable connections in the field. But you need to qualify. Last time, VSD generated 10 analogue IPs as a part of a FREE research program, which is currently the basis of many educational programs globally. And participants who built the IPs are either doing great in top tier 1 companies OR got admitted to Masters/PhD programs in top universities globally. Note - When we mention "*Tier 1*" and "*Top Universities*", we claim this with valid data. To know the name of companies and universities, you might want to search for TOP VLSI companies and TOP VLSI universities in the world, and you would find VSD research program participants This time, we will be introducing Physical design-based research problem statements (and there are many). But to attempt those, you need to complete the workshop 100%. To make sure, everyone gets an opportunity to join the research program, the workshop is charged nominally (we can't keep it for free, but we want many participants to attempt it) Don't miss out on this opportunity to take your physical design skills to the next level. Register for the OpenLANE Physical Design workshop today and you could be one of the lucky participants chosen to work on our VSD research program. Workshop registration details- https://www.vlsisystemdesign.com/advanced-physical-design-using-openlane-sky130/

<!channel> - Upgrade Your Physical Design Skills and Join Our Free Research Program We hope you're as excited as we are about the upcoming OpenLANE Physical Design Workshop! We wanted to remind you that by successfully completing the workshop, you'll have the opportunity to work on a cutting-edge VSD research program designed around mixed-signal physical design problem statements - and the best part is, it's completely free! In the workshop, you'll receive hands-on training and real-world examples from expert instructors in the field of physical design. You'll learn about the latest technologies used in the industry and how to use them to improve your workflow and productivity. But that's not all. If selected, by participating in our research program, you'll have the chance to apply the skills you learned in the workshop to real-world problems and help shape the future of the semiconductor industry. You'll also have lifetime access to the latest open-source tools and technologies used in physical design since they are open-source, giving you a competitive edge in the industry and building more chips for your personal research The workshop is heavily discounted, so all of you can join, but the follow-up 10-week research program for selected participants is completely free. Don't miss out on this opportunity to take your physical design skills to the next level and work on cutting-edge research. Sign up for the workshop today and join our research program starting February free. You can find workshop details in below link https://www.vlsisystemdesign.com/advanced-physical-design-using-openlane-sky130/ Best, Kunal Ghosh P.S. People have started to enrol and spaces are limited, so be sure to sign up soon to secure your spot!

<!channel> Previous OpenLANE Physical design workshop participants must have received an email from me regarding the VSD Research internship. Please fill up the form and we will share all relevant details. For freshers, who want to join the VSD research program, here's the last day for the Physical design workshop registration. Participants who complete the workshop will be directly selected for VSD hard-core research program https://www.vlsisystemdesign.com/advanced-physical-design-using-openlane-sky130/ Get ready for "less" certification and "more" mixed-signal PD Research Program. VSD will provide work-experience certificates once you complete the research program. All the best and happy learning

<!channel> Limitations of GPT-like Models in IC Design Process and need of opensource PDKs/VSD-HDP ChatGPT, as a language model, may not be able to replace VLSI physical design engineers, STA engineers, analogue designers, and physical verification engineers for several reasons. One reason is that the IC design process is highly complex, which is quite evident from past VSD-HDP participants and requires a deep understanding of the underlying technology, and process nodes, as well as the ability to make decisions based on trade-offs between different design constraints. GPT-like models can assist in automating certain tasks, but they are not yet able to replicate the level of expertise and decision-making capabilities of human engineers. Another reason is that the PDKs (Process Design Kits) used in the IC design process are often proprietary and not available to the public. This makes it difficult for GPT-like models to access the necessary information to perform the tasks required in IC design. This is where there is a need for opensource PDKs like SKY130 and there is a huge demand for people who understand production-grade PDKs, which is a core topic in VSD-HDP Additionally, VLSI design is an iterative process, and it can take multiple rounds of design, simulation, and verification to arrive at the final product. GPT-like models are not able to perform these tasks as well as human engineers, as they cannot use their intuition and experience to make design decisions that can save time and resources in the process. This is the exact point where we need open-source EDA tools and even more users who understand open-source and proprietary EDA tools usage. VSD-HDP currently focuses on the open-source EDA toolchain, which is the best place to start and is completely under your control. Furthermore, physical design engineers, STA engineers, analogue designers, and physical verification engineers are responsible for ensuring that the IC design meets the required specifications and constraints. This requires a deep understanding of the underlying technology, as well as the ability to use specialized software and tools to verify the design. GPT-like models may not have the same level of expertise and understanding of the technology and tools used in the IC design process. This is where we need a lot of open-source IPs, which again is a core area of focus in VSD-HDP. Finally, it is worth mentioning that the use of GPT-like models in VLSI physical design and STA tasks is a rapidly evolving field, and it is possible that in the future, these models may become more advanced and capable of taking on a greater role in the IC design process. However, it is unlikely that they will fully replace human engineers shortly. Learn more in the upcoming VSD-HDP and embrace AI as it's going to be the next cutting-edge solution which would help VLSI engineers. Here's the registration link https://www.vlsisystemdesign.com/hdp/ Your best bet to remain irreplaceable in the VLSI job market - Learn and innovate as much as you can using opensource All the best and happy learning

<!channel> There are many questions about the VSD-HDP curriculum. We recorded a short 5-minute video during a workshop call that goes into detail about the HDP curriculum, which addresses many frequently asked questions. Here is a link to the video snippet. Take a look and let us know if you have any further questions or concerns. VSD-HDP Registration link- https://www.vlsisystemdesign.com/hdp/

@Daniel Mateos Romero has left the channel

<!channel> VLSI Design RTL2GDS Mastery: Last 4 days, Enroll Today! In just 4 days, registration for our comprehensive HDP course on VLSI design will close. This course covers everything from architectural design to routing, providing you with a thorough understanding of the entire VLSI design process. Our experienced system engineer will walk you through the process of physical constraints and micro-architecture modelling, ensuring that you understand the specifications required for your circuit design. Additionally, you'll learn the importance of RTL design and behavioral modelling using Verilog, and the techniques used in RTL verification. The course also covers critical steps such as logic synthesis, post-synthesis STA analysis, floor-planning, placement, clock tree synthesis (CTS), and routing. You'll gain practical knowledge on how to plan the silicon area, create a robust power distribution network, and implement interconnect systems between standard cells. In this comprehensive course, you'll not only learn the key concepts of VLSI design, but you'll also gain hands-on experience with the industry-standard process-driven approach (see image). This approach is widely used in the industry and will give you a deeper understanding of how to design, verify, and implement complex VLSI systems. Don't miss this chance to take your VLSI design skills to the next level. Register now before it's too late! Registration link https://www.vlsisystemdesign.com/hdp/ All the best and happy learning

<!channel> Master the Art of STA with Our Hands-On 70% Discounted Workshop Great news for VLSI enthusiasts! An upcoming workshop offers the perfect opportunity to master the art of Static Timing Analysis (STA) with a comprehensive and hands-on training program. This workshop provides a solution to the challenges faced by both freshers and professionals in the field, and is designed to equip individuals with the necessary skills and knowledge to perform STA effectively. Static Timing Analysis (STA) is an essential step in the design flow of VLSI circuits. It involves verifying the timing constraints of a digital circuit to ensure it meets the performance requirements. However, performing STA can be a challenging task, especially for freshers and professionals who are new to the field. The challenges faced by freshers and professionals while performing STA include: 1. Lack of knowledge: For freshers, the biggest challenge is the lack of knowledge and understanding of STA concepts, techniques, and tools. They require a solid foundation in digital design and timing concepts to effectively perform STA. 2. Complexity of circuits: With the increasing complexity of VLSI circuits, the number of timing paths to be analyzed has also increased, making STA a more challenging task. 3. Timing constraints: Determining the correct timing constraints for a design can be difficult, especially for complex circuits, and requires a thorough understanding of the circuit's behavior. 4. Tool accuracy: STA tools are not always accurate, and incorrect results can lead to wrong conclusions, leading to potential design errors. 5. Time-consuming process: STA is a time-consuming process, and with the increasing size and complexity of VLSI circuits, it becomes even more challenging to perform the analysis within the required timeframe. To overcome these challenges, an upcoming STA workshop offers a solution by providing a comprehensive and hands-on training in Static Timing Analysis. The workshop covers both theoretical concepts and practical techniques, and covers the latest methodologies used in STA. This will give freshers and professionals a solid foundation in STA and provide them with the necessary skills and knowledge to effectively perform the analysis on complex VLSI circuits. By participating in the workshop, individuals can improve their STA skills and knowledge, and stay up-to-date with the latest developments in the field. The comprehensive training program will provide participants with a better understanding of the challenges faced in STA, and equip them with the necessary tools and techniques to overcome these challenges. In conclusion, the upcoming STA workshop offers a unique opportunity for freshers and professionals to enhance their skills and knowledge in Static Timing Analysis. By participating in the workshop, individuals can improve their ability to perform STA effectively, and increase their chances of success in the VLSI design industry. So, register now to take advantage of this opportunity! Registration closes in 4-days https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/

<!channel> Only 5 days left - Step Up Your STA Game with Our 70% Discounted Professional Training The world of digital VLSI design is constantly evolving, and keeping up with the latest techniques and tools is essential for success. The STA workshop provides a comprehensive and hands-on approach to learning about STA, making it the perfect opportunity to gain a deeper understanding of this critical aspect of digital design. The workshop will cover a wide range of topics. Below are the some topics from Day 1 of the workshop: 1. STA Definition: STA stands for Static Timing Analysis. It is a verification methodology used in digital VLSI design to determine the timing characteristics of a digital circuit. It is used to determine the timing margins of a design and ensure that the design meets the specified timing requirements. 2. Timing Paths: Timing paths are the sequences of gates and interconnects in a digital circuit that transmit a signal from its source to its destination. The timing of a path is the time taken for the signal to travel from source to destination. 3. Timing path elements: The timing path elements are the individual components (gates, interconnects, flip-flops, etc.) that make up the timing path. The timing of each element affects the overall timing of the path. 4. Setup & Hold Checks: Setup and hold checks are critical to STA. The setup time is the amount of time before the clock edge that a signal must be stable for it to be captured correctly. The hold time is the amount of time after the clock edge that the signal must remain stable for it to be captured correctly. 5. Slack Calculation: Slack is the amount of time by which a timing path meets or violates its specified timing requirement. Positive slack indicates that the timing path meets its requirement, while negative slack indicates that the timing path violates its requirement. Slack calculation is an important aspect of STA as it helps determine the timing margin of a design. 6. SDC Overview: SDC stands for Synopsys Design Constraints. It is a constraint file that provides information about the timing requirements of a digital design. The SDC file is used as input to STA tools to perform timing analysis. 7. Clocks: Clocks are a fundamental aspect of digital design, as they synchronise digital circuits' operations. The frequency and duty cycle of clocks are critical factors that affect the timing of digital circuits. 8. Generated Clocks: Generated clocks are clocks that are derived from other clocks in a digital design. They are used to generate specific clock signals for different parts of the design. 9. Boundary Constraints: Boundary constraints are timing requirements that are specified at the boundary between different blocks or modules in a digital design. These constraints are used to ensure that the timing of the blocks meets the specified requirements and that the blocks operate correctly together. The OpenSTA tool is a powerful and widely used opensource tool for STA, and the workshop will provide a comprehensive introduction to its usage and capabilities. You will learn about the inputs required for OpenSTA, how to create constraints for your design, and how to run the OpenSTA script to perform timing analysis on your design. With the knowledge and skills gained from this workshop, you will be well-equipped to perform STA on your own designs with confidence. Registration closes in 3 days. Here's the link with more details: https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/

<!channel> Optimizing Chip Performance: The Importance of Static Timing Analysis (STA) workshop There were queries from freshers regarding the upcoming STA workshop and its importance. So, this time, let me try to cover the importance of STA in below blog Static Timing Analysis (STA) is a crucial step in analyzing the performance of a chip, as it allows engineers to optimize the timing of their design to ensure that it operates at maximum efficiency. In this blog, we will explore why STA is needed for analyzing a chip's performance and how it is used in the VLSI design process. The workshop will cover every item in detail in form of hands-on labs First, let's define what we mean by chip performance. In the context of VLSI design, chip performance refers to the speed and power consumption of the chip. These factors are critical to the success of the design, as faster and more power-efficient chips are generally more desirable. Now, let's consider why STA is necessary for analyzing chip performance. In simple terms, STA is used to ensure that the timing of the chip is optimized for maximum speed and power efficiency. It does this by analyzing the critical paths in the chip, which are the paths that determine the overall timing of the design. During the STA process, engineers use industry-standard tools to simulate the chip and measure the timing of the signals as they travel through the design. This information is then used to identify the critical paths and analyze their timing parameters, such as setup time, hold time, and clock skew. The results of the STA analysis are then used to optimize the timing of the critical paths. This might involve adjusting the clock frequency or changing the design of the logic gates to reduce delays. By optimizing the critical paths, engineers can ensure that the chip operates at maximum efficiency, with minimum power consumption and the fastest possible speed. STA is a vital part of the VLSI design process, as it enables engineers to identify and optimize the timing of their designs. Without STA, designers would have to rely on trial and error to identify the critical paths and optimize the timing of their chips, which would be a time-consuming and inefficient process. In conclusion, STA is essential for analyzing the performance of a chip, as it allows designers to optimize the timing of their designs for maximum speed and power efficiency. By analyzing the critical paths in the design and optimizing their timing parameters, *designers can ensure that their chips operate at maximum efficiency and meet the performance requirements of their target applicatio*n. So, if you're a VLSI engineer, make sure to include STA in your design process for optimal chip performance. Does that sound interesting? Join us for our upcoming VLSI STA workshop and gain hands-on experience with open-source tools OpenSTA and manufacturable SKY130 PDKs. You'll learn from the best and gain practical skills that will set you apart from the competition. Here's the registration link: [Registration closes in 48hours] https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/ All the best and happy learning

<!channel> Last Chance to Enroll in our STA Workshop We are pleased to announce our upcoming STA Workshop, and we don't want you to miss out on this fantastic opportunity to upskill your knowledge in this field. If you're passionate about VLSI Design and want to excel in Static Timing Analysis, then this workshop is perfect for you. To sweeten the deal, we are offering an exclusive 70% discount on the workshop fee, but here's the catch - this offer expires in the next 12 hours! So, you need to act fast to grab this opportunity. Our workshop is led by industry experts and covers various aspects of Static Timing Analysis, including T*iming Analysis Flow, Clock Tree Synthesis, and many more*. You will gain hands-on experience and learn through interactive sessions that will help you apply the knowledge you gained in real-world scenarios. To enroll, visit our website and complete the registration process. The discount will be applied automatically at the checkout page, and you will be able to see the reduced fee. Don't miss this fantastic opportunity to upskill yourself and become an expert in STA. If you have any questions or concerns, please don't hesitate to contact us. Our friendly TA team is always ready to assist you. Thank you for considering our workshop. We hope to see you soon! Here's the registration link- https://www.vlsisystemdesign.com/sign-off-timing-analysis-basics-to-advanced/ All the best and happy learning

@Ben has left the channel

<!channel> From Software to Silicon: The fusion of Programming and Chip Design Calling All Software Developers: Join the open-source chip design movement and expand your skill set! To facilitate software developers, you will get FREE access to VSD's Online Physical Design course on Udemy during the event to discover the exciting world of chip design. If you're a software developer looking to explore a new world of innovation, consider joining the 7nm open-source chip design movement. There's never been a better time to leverage your modern software practices into chip design and push the limits of what can be done. In the world of chip design, there has been a growing movement towards embracing open-source tools and practices. The goal is to lower the barriers to access to silicon, while also pushing the limits of what can be done. Leveraging modern software practices in chip design is becoming more common, and open-source electronic design automation (EDA) tools and process design kits (PDKs) are becoming key components of research. One of the advantages of the open-source chip design ecosystem is that it encourages reproducibility and reuse, leading to great educational content available online to everyone. Additionally, this ecosystem facilitates the development of the accompanying EDA tooling and open-source register transfer language (RTL) by a greater number of individuals. While free software has been a component of the software industry for many years, a movement has begun among hardware developers to offer the same access to source material relating to chip design. Many behaviours in the hardware world are changing right now and adopting more of a software mindset. With open-source tools, you can audit the code and see exactly what you have on your chip, which gives you control over the toolchain. An important program initially funded by the government to facilitate open-source chip design is known as OpenROAD. Led by Professor Andrew Khang at UCSD, the OpenROAD project was initiated to provide open-source semiconductor design automation tools. The goal is to develop an entirely open-source semiconductor manufacturing workflow. To promote this vision, the OpenROAD 7nm Physical Design Contest was created to showcase the benefits of open-source tools and practices. The contest features interesting design challenges at an advanced technology node (7nm) and is organized by The OpenROAD Project and VLSI System Design (VSD) This unique event provides a platform for software developers to delve into the exciting world of chip design. With a focus on using programming skills to create cutting-edge chip designs, this event is the perfect opportunity for those with an electronics background who have transitioned to software. Don't miss this chance to explore a new frontier and take your programming skills to the next level. Register now to join us for this game-changing event! Register for the event using the below link: https://www.openroaddesigncontest.org/ All the best and happy learning

<!channel> Breaking the Mold with Open-Source VLSI: Meet the Expert Speakers of the OpenROAD 7nm Physical Design Contest! Are you ready to break barriers with Open-Source VLSI? We're thrilled to announce the expert speakers for our upcoming design contest who will guide you to the top. We have Prof. Andrew Kahng and Tom Spyrou from The OpenROAD Project, UC San Diego, Angada Sachid from Intel Corporation and Øyvind Harboe from Ascenium Inc onboard. Their direct experience and skills related to the contest will provide the insight needed to determine the winners. With their vast knowledge and experience, you'll be inspired to put your best foot forward and join the excitement. Don't miss the OpenROAD 7nm Physical Design Contest and be part of an unforgettable experience! Here's the registration link https://www.openroaddesigncontest.org/

<!channel> How OpenROAD Facilitates the Implementation of Open-Source RISC-V Cores Ibex and Swerv_wrapper Are you ready to put your physical design skills to the test? If so, the upcoming 7nm OpenROAD Physical Design Contest might just be the challenge you're looking for! This exciting contest provides an opportunity for engineers and designers to showcase their talents and innovation by tackling real-world design problems using the latest open-source tools and technology. The OpenROAD Project platform is transforming the world of hardware design by developing open-source tools that enable no-human-in-loop, 24-hour layout implementation. This breakthrough approach removes the barriers to innovation that arise from high costs and expertise gaps, making it easier for engineers to develop advanced technology. With the help of OpenROAD, it's now possible to implement open-source RISC-V cores like Ibex and Swerv_wrapper with ease, streamlining the design process and democratizing hardware design. By creating an open and accessible design platform, the OpenROAD team is empowering hardware designers to achieve their goals without needing to be experts in advanced technology. The platform is designed to be fully tapeout-capable, with source code tools available under permissive licensing to enable widespread use. OpenROAD's ultimate goal is to create a new "Linux of EDA" by developing new base technologies that enable 24-hour, autonomous design. Through extreme partitioning, parallel search and optimization, machine learning, and a new paradigm for design tools and methods, OpenROAD is breaking down barriers and paving the way for a new era of hardware innovation. Whether you're an experienced physical design expert or a newcomer to the field, this contest is a fantastic way to push your limits and test your abilities. With the support of the OpenROAD community and access to cutting-edge design tools, you'll have everything you need to bring your ideas to life and create innovative solutions that could shape the future of the semiconductor industry. So, what are you waiting for? Join the contest and take your physical design skills to the next level! Participate in the upcoming "*The OpenROAD 7nm Physical design contest*" to know many more exciting features about OpenROAD https://www.openroaddesigncontest.org/

@vks has left the channel

<!channel> Make Your Mark in VLSI Physical Design: Join the OpenROAD EDA Contest and Contribute to Open-Source Looking for ways to up-scale your physical design and EDA career? Look no further than the upcoming contest, which offers a range of exciting problem statements that will challenge you and allow you to showcase your skills. Take, for instance, enhancing the OpenROAD GUI Flow Manager by developing custom features for analysis and visualizations. You'll support native and third-party flows, including OpenROAD-flow-scripts, and others. This is an excellent opportunity to create documentation, commands, developer guide notes, and tutorials to show GUI usage for supported flows. Another contest problem statement is profiling and tuning the OpenROAD flow for runtime improvements. You'll develop verifiable and reproducible strategies to improve run times in OpenROAD-flow-scripts. This includes optimizing computational resources over the cloud, tuning algorithmic and design flow parameters, and creating test plans using existing or new designs to show runtime improvements. You can also update OpenROAD documentation and tutorials by reviewing and updating missing documentation and tutorials in OpenROAD-flow-scripts for existing and new features. You can test the accuracy of generated LIB and LEF models for signoff in OpenROAD-flow-scripts for flat and hierarchical design flows. Build test cases to validate and add to the regression suite. With so many exciting challenges, this contest is the perfect opportunity to join, collaborate, contribute, learn, and achieve new heights in your VLSI career. If you're looking to take your physical design and EDA career to the next level, then this contest is your best chance to do so. Don't miss out on the chance to upscale your skills and showcase your talent. Check out the contest and join other participants who have already started contributing to the 7nm OpenROAD flow. The sky's the limit for a successful VLSI career! Register for FREE using the below link: https://www.openroaddesigncontest.org/

<!channel> Thanking Our Generous Sponsors for the 7nm OpenROAD Physical Design Contest We are grateful to our sponsors for the 7nm OpenRoad physical design contest. We appreciate their support for this event and their generosity in sponsoring the winners. First, we would like to thank Prof Andrew Kahng, a Distinguished Professor of CSE and ECE at UC San Diego. He is a renowned expert in the field of IC physical design and performance analysis, and his contributions to the field are immeasurable. We are honoured to have him as a sponsor and a part of this event. Next, we would like to thank Indira Iyer, Head of User Experience and Outreach at Precision Innovations. Her expertise in building local and international alliances/partnerships, channel/distribution ecosystems for disruptive products and services, and structuring large machine and deep learning systems for product innovation and scale is invaluable. We are grateful for her support and sponsorship of this event. Finally, we would like to express our appreciation to Øyvind Harboe from Ascenium. His engineering management expertise and leadership have been instrumental in creating the breakthrough general-purpose computing technology at Ascenium. We are honoured to have Ascenium as a sponsor, and we look forward to collaborating with them in the future. Their support and trust in this event have made it possible for us to provide a platform for innovative and talented individuals to showcase their skills and expertise in the field of IC design. We appreciate their commitment to advancing the semiconductor industry and their dedication to supporting emerging talents. With their support, we are confident that this contest will be a tremendous success and help shape the future of IC design. We look forward to continued partnerships with our sponsors as we continue to provide opportunities for the next generation of innovators. Sponsors can make a significant difference in the lives of students by helping those who are in need and those who have great potential to learn and achieve great heights. Once again, we extend our heartfelt gratitude to Prof Andrew Kahng from UCSD, Indira Iyer from Precision Innovations, and Øyvind Harboe from Ascenium for their unwavering support and dedication to this event. Thank you for your generosity, and we hope to continue our partnership for years to come. Register for the contest using the below link: https://www.openroaddesigncontest.org/

<!channel> Complete Your Industry VLSI Curriculum with This Comprehensive Verilog HDL Workshop! The Verilog HDL Digital Design Workshop: From Fundamentals to Complex Circuits is your ultimate guide to mastering the art of digital circuit design. This 5-day workshop is jam-packed with comprehensive and hands-on training that will equip you with the skills you need to design and implement a diverse range of circuits, including combinational and sequential circuits, state machines, and memory circuits. On Day 1, you'll receive an introduction to digital design, including datatypes and operators. Then, on Day 2, you'll dive into Combinational Logic, where you'll learn about the basics of combinational logic design and how to use combinational logic gates to design circuits. Day 3 focuses on Sequential Design, where you'll learn about sequential logic design using Verilog HDL, including designing sequential circuits using flip-flops and implementing them in Verilog. On Day 4, you'll move on to Complex Sequential Logic and State Machines, where you'll learn how to design complex sequential circuits such as counters, shift registers, and state machines using Verilog HDL. Finally, Day 5 covers the design and implementation of First-In-First-Out (FIFO) and Random Access Memory (RAM) using Verilog HDL. You'll also learn how to design state machines to control the operation of these circuits. Throughout the workshop, you'll have the opportunity to apply what you've learned through hands-on lab exercises in Verilog HDL. This practical experience will enable you to confidently apply your knowledge in real-world situations. By the end of the workshop, you'll have gained a comprehensive understanding of digital logic design using Verilog HDL. You'll be equipped to design and implement a wide range of digital circuits and will have the practical experience necessary to apply your knowledge in real-world scenarios. Don't miss out on this valuable learning opportunity – sign up for the Verilog HDL Digital Design Workshop today using the below registration link! https://www.vlsisystemdesign.com/verilog/ All the best and happy learning

<!channel> We are thrilled to have partnered with Indian Institute of Technology, Madras and Digital India RISC-V (DIR-V) to launch vsdsquadron - an exceptional educational board for RISC-V learning and VLSI chip design. With "vsdsquadron", aspiring chip designers can gain practical experience and skills required to excel in the semiconductor industry. Our collaboration with IIT Madras, the pioneers behind India's first microprocessor Shakti, has allowed us to create a platform that utilizes open-source design flow and PDKs, setting a new standard in chip design education. We are proud to be a part of India's journey towards a self-reliant technology sector and invite you to join us on this exciting path of innovation and excellence. Read below blog for more details- (Limited to 200 Seats) RISC-V Roadshow on Shakti Ideology at IIT Madras on 27th April, 2023

<!channel> ALIGN Open-Source Tool for Analog Circuit Layout Synthesis: Hands-on Lab-based Training Webinar If you're a circuit designer looking for a more efficient way to synthesize analog circuit layouts, then you won't want to miss this free webinar on the ALIGN open-source tool. Developed by a team of academics and industry professionals, ALIGN is an automatic layout generator that can translate an unannotated SPICE netlist into a GDSII layout in just 24 hours. In this webinar, we'll be discussing how the ALIGN tool works and how it can be used to synthesize the layout for a 4-bit asynchronous up counter. This mixed-signal circuit is designed using xschem and Ngspice tools and features T flip-flops, a ring oscillator, an ADC, and a DAC. The webinar will cover a range of topics related to the ALIGN project, including design specifications, an introduction to ALIGN, installation of ALIGN prerequisites, ALIGN installation, ALIGN SKY130 installation with a buffer example, and pre and post-layout analysis of a ring oscillator and ADC using ALIGN. One of the benefits of ALIGN is that it's an open-source tool, meaning that it's freely available to use and modify. This makes it an excellent resource for designers who are looking for a more customizable and efficient way to synthesize analog circuit layouts. Additionally, the ALIGN tool was jointly developed under the DARPA IDEA program by the University of Minnesota, Texas A&M University, and Intel Corporation, so you know that it's been rigorously tested and optimized for real-world use. Webinar registration from - https://forms.gle/Dh6EKHNv59Wgw1Ku9 Webinar Dates and Timings - 2nd May, 8pm to 9pm IST To enroll in this free webinar and learn more about how ALIGN can help you with your analog circuit layout synthesis, simply click on the link below. We look forward to seeing you there! Once you fill the form, you will receive meeting invitation

<!channel> Invitation to Join Our Free Webinar on OpenFASoC and ALIGN for Chip Core Generation, by VSD Intern VSD interns are performing exceptionally well. We are pleased to invite you to a free webinar where we will be discussing the innovative use of OpenFASoC and ALIGN tools for generating a complete core for a chip. This webinar aims to provide valuable insights into the process of designing analog blocks using Xschem, ALIGN, and Magic, as well as the significance of verilog files in linking various components of the OpenFASoC flow. Webinar Details: Date: 18th May Time: 8pm IST Duration: 1-hr Agenda: 1. Introduction to OpenFASoC and ALIGN: Learn about these powerful tools and their role in generating a complete core for a chip. 2. Analog Block Generation with Xschem and ALIGN: Discover how Xschem is used to generate schematics and how ALIGN, along with Magic, aids in designing the layout for the analog block, specifically focusing on the creation of a self-toggling circuit called a ring oscillator. 3. 1-Bit ADC Analog Block Generation: Explore the process of using Xschem, ALIGN, and Magic to generate the schematic and layout for the 1-bit ADC analog block. 4. Verilog Files and OpenFASoC Flow: Understand the crucial role of verilog files in correctly linking the GDS and LEF files within the OpenFASoC flow. Learn about the top-level verilog file, "async_up_down.v," and the two macros, "COMPARATOR.v" and "RING_OSCILLATOR.v," which correspond to the cell names given in the GDS. 5. Flow Overview: Gain insights into the complete chip core generation flow, including steps such as Verilog cleaning and synthesis, APR, floorplanning, global placement, detailed placement, global routing, antenna check, and DRC check. Our expert speaker will walk you through each step, providing practical tips and insights gained from real-world experiences. This webinar is ideal for chip designers, engineers, and enthusiasts who want to expand their knowledge of core generation using OpenFASoC and ALIGN tools. To reserve your spot, please click on the following registration link: https://forms.gle/EuFYSFNnURykpfLg8 Don't miss out on this fantastic opportunity to enhance your chip design skills and learn about the latest advancements in core generation. We look forward to your active participation in the webinar.