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What is the default user clock frequency, like if I changed nothing after cloning the caravel repo what would user_clock2 and wb_clk_i run at when I get the chip?
Sim shows 40MHz, documentation says external clock is 12.5 MHz but the CPU runs at 100MHz, the openlane folder sets the port clock period to 10 (100MHz?), I don't know whats the real value

its configurable by software. You can chanchge the PLL settings in firmware.

I would not rely on that clock as it is not very stable

frequency wise. But if you need any clock, this will suffice

Thanks for answering quickly, do you mind me asking what do you mean by it is not stable? And what clock are you referring to when you say "that clock"

Also I just realized, that doesn't answer my question, by default if I change nothing what will the frequency be

Yes, I didnt give you a number, because answer depends on what firmware you will load to the caravel. The docs does not specifically mention the default value AFAIK but has maximum of value 40MHz in absolute rating.

By "not stable" I mean, frequency, duty cycle and phase shifts a lot. Its a digital PLL at the end of the day. A lot in this context means significantly higher than PLL in FPGAs I used. e.g. 50 ppm, while caravel unlikely to deliver anywhere close to it.

Also it refers to both clocks. They are driven from the same PLL but AFAIK have different dividers

<https://github.com/efabless/caravel_board/search?q=pll&amp;type=|https://github.com/efabless/caravel_board/search?q=pll&amp;type=>

<https://caravel-harness.readthedocs.io/en/latest/external-clock.html|https://caravel-harness.readthedocs.io/en/latest/external-clock.html>

This page suggests that the default clock is the external clock signal

<@U040Z2QKE9J>:  The CPU does not run at 100MHz.  It is characterized for 40MHz maximum.  The clock that his shipped on the board runs at 10MHz.  The `user_clock2` is provided for the purpose of providing a clock into the user project that is higher than 40MHz, since the only other clock is `wb_clk_i` and comes from the CPU, so if it gets higher than 40MHz the CPU will stop running and so will the clock.  The DLL (measured on MPW-two silicon) runs from 40MHz to 95MHz.  It should not be called "unstable"---strictly speaking, it has high phase noise or cycle-to-cycle jitter because it shortens or lengthens individual cycle times to stay frequency-locked to the reference input.  It can also be run in DCO mode (no reference input) which has low cycle-to-cycle jitter but does not have any temperature compensation.

By default both clocks (`wb_clk_i` and `user_clock2`) are connected directly to the input on the clock pin, so with an unmodified board, both will be running at 10MHz.

Alright thanks guys, that helps clarify some things