Hello @Akash Levy could you please give some suggestions regarding the design of a sense amplifier for ReRAM read operations involving multiple bits read within a 2x2 array, as well as the determination or calculation of voltage references for sense amplifier .

Yes please look at the RRAM guide I sent earlier. I will see if I can find it and link it again

Thank you @Akash Levy i have read that but I am confused for reference voltage how to define for multiple bits per cell for reading so I am looking more information to understand and read how to define voltage references .

There's lots of ways you can do reference voltages/resistors. I'm not too familiar with the best way to do voltage mode sensing, @Luke Upton might know. For current mode, you would use reference resistors and you can use something like R2R ladder (there are lots of good ways to do it). https://en.wikipedia.org/wiki/Resistor_ladder I'd recommend picking up an analog design textbook and/or taking an analog design course for this. Building DACs/ADCs are usually a core concept

Thank you one of the other way I saw is the circuit I have attached in the picture. I have concern with the values of the voltage for references . @Luke Upton it would be great if could give suggestions. For multiple bits what would be the voltage values for reference in sense amp for that do I need make simulation and get the set points then calculate and set the values of reference voltage ?

The pictured sense scheme looks like it takes the current from sensing multiple cells in parallel and converts that to a voltage at the comparator input. There is likely a cascode NMOS being used to force a known read voltage across the RRAM so that the parallel resistance of the cells can be calculated. Then this Vread/Rcells current is pulled across a known resistance (like the pull-up PMOS devices in https://ieeexplore.ieee.org/document/8662393) to generate a voltage at the "Vin" side of the voltage comparator in a sense amplifier. The input voltage for the opposite side of the comparator is determined by 1) the read voltage you use for sensing the RRAM (highly advise matching the read voltage on the RRAM side) and 2) the resistance "steps" you want to compare against your RRAM with. You can then estimate those ref voltages at the comparator input with Vread/Rref * Rout. So you can use a resistor bank to generate the ref currents by mimicking the RRAM read voltage drop across the resistors or you could use a voltage DAC to generate the estimated voltage seen if you were to do the read voltage drop across the resistors. The replica resistance with a Vread would probably track better across temperature and process compared to the voltage DAC method though.

Thank you @Luke Upton