Does anyone know of a way in SystemVerilog to restrict access to a local variable? For example I have

module dut();
  logic dont_look_at_me;
endmodule

and

module testbench();
  dut inst();
  initial begin
    $display ("%i", inst.dont_look_at_me)
  end
endmodule

Is there a way in either the language or the simulator (VCS) to force a compilation error on

dut.dont_look_at_me

?