@Luis Henrique Rodovalho I have a question on the images you made for the debug of issue #380. In the plot below what was the expected result? It’s supposed to be a line with a constant positive slope, right? (for NMOS) I’m guessing it’s based on the idea that for fixed Vds, Vds=Vgs and Vbs=0 then Ids = (W/L)[X1-Vt(L)]X2 (with X1 and X2 being whatever constants) so by plotting Ids*L one cancels out the effect of varying L, except for the variation of Vt which is a function of channel length. But maybe the higher level spice models have parameters related to manufacturing that can make this more parabolic? Basically this is a super long winded way of asking, can @proppy check the model for discontinuities by ensuring d(ID*L)/dL is constant?

I would not expect d(ID*L)/dL to be constant, but it should not have odd discontinuities as seen here.

The canonical dependence of MOS current on W/L is valid for large geometries. At small geometries there are many non linear effects, like threshold shift, carrier velocity saturation, and many more. As a result the Id * L vs L is constant for large L. Picture shows Id at Vg=Vd=0.8, 1.0, 1.2, 1.4, 1.6, 1.8V for a W=1u Nfet_01v8.

There are some short channel effects that are modeled as a deltaVT as function of L. A 1.0um/0.5um is not the same as a 2.0um/1.0um. Those transistors have the same aspect ratio, but their VTs are different. The problem is that the VT variability is a smooth function for each bin. When there is a transition from bins, the models are different and there are discontinuities. GF180 models are much better in this aspect, but there are less bins and its smaller L is 280n.