How to make OpenLane synthesize System Verilog(.sv...
# sky130t
Thouheed
10/12/2022, 5:35 AMHow to make OpenLane synthesize System Verilog(.sv) along with verilog.
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Vijayan Krishnan
10/12/2022, 5:40 AMconvert your .sv to .v using sv2v tool and use with OpenLane flow
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Thouheed
10/12/2022, 5:49 AM@Vijayan Krishnan
https://github.com/zachjs/sv2v
Am i referring the correct repo?
v
Vijayan Krishnan
10/12/2022, 5:49 AMyes
👍 1
Vijayan Krishnan
10/12/2022, 5:56 AMOnly few SV features not supported with current yosys.
Did you synthesized and facing any issues with sv files?
m
Michael Strothjohann
10/12/2022, 2:46 PMFor an up-to-date comparison between different opensource sv2v translators (and sv-parsers):
https://chipsalliance.github.io/sv-tests-results/
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