My complete design will be digital-on-top but I also have analog components that I want OpenLane to route together with the digital parts. Can anyone provide me with an outline of how to do this please?

1. Make lefs of the analog cells 2. Connect analog cells using EXTRA_LIBS, EXTRA_LEFS and EXTRA_GDS. Libs might be skipped but then timing is not checked 3. It should auto place the cells, but if it does not use macro placement cfg 4. run the flow and debug the issues: Examples for hierarchical and OpenRAM: https://github.com/The-OpenROAD-Project/OpenLane/pull/1351

Thank you very much for this fast and detailed reply!

@Christof Gindu You can check our last submission, here we combine a digital block with an analog one in OpenLane and prepare for MPW-5 submission: https://github.com/iic-jku/iic-audiodac-v1

perfect, thank you very much Mr. Pretl!

You have to harden analog and digital blocks separately. GDS for both of them will be created. Then integrate all the GDSs in the top level. Use the coordinates properly in the macro.cfg

Hi @Harald Pretl, I've checked your MPW-5 submission as guide for integrating an analog macro, it has been super helpful, the macro appears in the user_project_wrapper and the analog pins connect just fine. There is something that I haven't been able to make work, which is connecting the analog macro to the analog power and ground rails. If metal 5 is used in the layout, it "repels" the PDN stripes of metal 5, so I tried leaving only up to metal 4 in the layout, but OpenLane (or OpenROAD) doesn't create the vias for making contact. How did you do it? It's something that has to be manually wired? Any advice would be appreciated

check my docs. They info why the vias are not added

@Norman Méndez As you mentioned, you should not use

metal5

inside the analog macro, and the

metal4

areas for the connection must be large enough so that the

metal5

strips from the PDN have a chance to hit them. Plus, I think you need to set

FP_PDN_MACRO_HOOKS

correctly, as @Arman Avetisyan writes in his doc (link above). Here is the example from our MPW-5 submission in `config.tcl`:

set ::env(FP_PDN_MACRO_HOOKS) "\
	dac0 vccd1 vssd1 \
	drv0 vdda1 vssa1"

Thank you @Arman Avetisyan and @Harald Pretl for your answers. The

FP_PDN_MACRO_HOOKS

configuration seems to be alright. Indeed it's a small macro, I've been playing with different layer sizes of metal 4 (last try was 130um x 150um on each

VDD

and

VSS

ports) so it could make contact with the metal 5 strips, but no luck whatsoever. I'll keep looking in my config in case I missed something else.

what is value of your DESIGN_IS_CORE?

Hi @Arman Avetisyan @Harald Pretl, I found my two silly mistakes, the power pin names in the blackbox verilog didn't match the ones in

config.tcl

(I thought that with the wiring in the

user_project_wrapper.v

was enough, I didn't understand what really meant the syntax of

<vdd_pin>

<gnd_pin>

until now) and there was an underscore on the name of the macro that wasn't present in the other references to that macro. I realized looking at the log

floorplan/6-pdn.log

that the analog macro power pins already didn't connect at that stage. Now it creates the vias correctly and passes the flow. Thank you both for your help!