Much more likely that it is a caravel RTL issue; we have always tested our code against iverilog simulation, so if iverilog is less strict about syntax, then errors may go undetected if yosys is also less strict (which it tends to be---it handles a lot of incorrect verilog smartly, probably mimicking similar behavior of other FPGA synthesis tools, whereas the ASIC synthesis tools tend to emit fatal error messages and halt). If at any time iverilog gets upgraded to be more strict about verilog syntax, then code in caravel is almost guaranteed to break.

Although this error looks more like a file was included twice.

Looking at it closer. . . So the problem seems to be that if something has been declared in the pin list, and subsequently the same signal name is declared a wire, this is what is suddenly throwing an error. I am not aware that that's an error in verilog, although there are at least three different versions of verilog and I don't know all the rule differences between them. But I am used to specifying outputs as either wires or registers within the body of the module and not inside the pin list. At least at first glance, it doesn't look like an error to me and I would call it an error that was introduced into iverilog. But I can't dismiss the possibility that the syntax actually is an error in one of the forms of verilog, and maybe the syntax checking has been tightened up and it might be necessary to change the verilog code accordingly or pass some switch to iverilog declaring the version of verilog syntax that is being used in the source.

(That is, if you pass the option switch, say,

-g2005-sv

to iverilog, does it stop complaining? Does iverilog have a new syntax option switch now? Previously it had

-g1995|-g2001|-g2005|-g2005-sv|-g2009|-g2012

, and I assume the default syntax used is the most recent syntax version.)